3x3 FPGA realization of median filter (VERILOG) source code integrity, and can be used directly.




File list:
Code_for_MedianFilter33
......................\MedianFilter
......................\............\comparator_mdf.v
......................\............\comparator_mdf.v.bak
......................\............\data_gen.v
......................\............\data_gen.v.bak
......................\............\drf1024x16.v
......................\............\drf896x16.v
......................\............\dsram1920x16.v
......................\............\edge_detect.v
......................\............\line_buffers_mdf.v
......................\............\median_filter.v
......................\............\rd_ctr_mdf.v
......................\............\top_median_filter.v
......................\............\wr_ctr_mdf.v
......................\............\yuv_data_out.v
......................\comparator_mdf.v
......................\data_gen.v
......................\drf1024x16.v
......................\drf896x16.v
......................\dsram1920x16.v
......................\edge_detect.v
......................\line_buffers_mdf.v
......................\median_filter.v
......................\rd_ctr_mdf.v
......................\top_median_filter.v
......................\wr_ctr_mdf.v
......................\yuv_data_out.v