here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily




File list:
Elham Zahraei Salehi_ Sina Saharkhiz
...................................\work
...................................\....\@a@l@u
...................................\....\......\verilog.prw
...................................\....\......\verilog.psm
...................................\....\......\_primary.dat
...................................\....\......\_primary.dbs
...................................\....\......\_primary.vhd
...................................\....\@branch@data@forwarding
...................................\....\.......................\verilog.prw
...................................\....\.......................\verilog.psm
...................................\....\.......................\_primary.dat
...................................\....\.......................\_primary.dbs
...................................\....\.......................\_primary.vhd
...................................\....\@branchpred
...................................\....\...........\verilog.prw
...................................\....\...........\verilog.psm
...................................\....\...........\_primary.dat
...................................\....\...........\_primary.dbs
...................................\....\...........\_primary.vhd
...................................\....\@controller
...................................\....\...........\verilog.prw
...................................\....\...........\verilog.psm
...................................\....\...........\_primary.dat
...................................\....\...........\_primary.dbs
...................................\....\...........\_primary.vhd
...................................\....\@data@memory
...................................\....\............\verilog.prw
...................................\....\............\verilog.psm
...................................\....\............\_primary.dat
...................................\....\............\_primary.dbs
...................................\....\............\_primary.vhd
...................................\....\@e@x_@m@e@m
...................................\....\...........\verilog.prw
...................................\....\...........\verilog.psm
...................................\....\...........\_primary.dat
...................................\....\...........\_primary.dbs
...................................\....\...........\_primary.vhd
...................................\....\@ex_@mem@data@forwarding
...................................\....\........................\verilog.prw
...................................\....\........................\verilog.psm
...................................\....\........................\_primary.dat
...................................\....\........................\_primary.dbs
...................................\....\........................\_primary.vhd
...................................\....\@i@d_@e@x
...................................\....\.........\verilog.prw
...................................\....\.........\verilog.psm
...................................\....\.........\_primary.dat
...................................\....\.........\_primary.dbs
...................................\....\.........\_primary.vhd
...................................\....\@i@f_@i@d
...................................\....\.........\verilog.prw
...................................\....\.........\verilog.psm
...................................\....\.........\_primary.dat
...................................\....\.........\_primary.dbs
...................................\....\.........\_primary.vhd
...................................\....\@instruction@memory
...................................\....\...................\verilog.prw
...................................\....\...................\verilog.psm
...................................\....\...................\_primary.dat
...................................\....\...................\_primary.dbs
...................................\....\...................\_primary.vhd
...................................\....\@p@c
...................................\....\....\verilog.prw
...................................\....\....\verilog.psm
...................................\....\....\_primary.dat
...................................\....\....\_primary.dbs
...................................\....\....\_primary.vhd
...................................\....\@pipe@reg1
...................................\....\..........\verilog.prw
...................................\....\..........\verilog.psm
...................................\....\..........\_primary.dat
...................................\....\..........\_primary.dbs
...................................\....\..........\_primary.vhd
...................................\....\@pipe@reg3
...................................\....\..........\verilog.prw
...................................\....\..........\verilog.psm
...................................\....\..........\_primary.dat
...................................\....\..........\_primary.dbs
...................................\....\..........\_primary.vhd
...................................\....\@porcessor_test
...................................\....\...............\verilog.prw
...................................\....\...............\verilog.psm
...................................\....\...............\_primary.dat
...................................\....\...............\_primary.dbs
...................................\....\...............\_primary.vhd
...................................\....\@processor
...................................\....\..........\verilog.prw
...................................\....\..........\verilog.psm
...................................\....\..........\_primary.dat
...................................\....\..........\_primary.dbs
...................................\....\..........\_primary.vhd
...................................\....\@register@file
...................................\....\..............\verilog.prw
...................................\....\..............\verilog.psm
...................................\....\..............\_primary.dat
...................................\....\..............\_primary.dbs
...................................\....\..............\_primary.vhd
...................................\....\_temp
...................................\....\.....\vlog1qa6kg
...................................\....\.....\vlog8f0g1q
...................................\....\.....\vlog9c26wi
...................................\....\.....\vlog9nizie
...................................\....\.....\vlogbi7zei
...................................\....\.....\vlogcxngxc
...................................\....\.....\vlogd5w4ib
...................................\....\.....\vlogeye447
...................................\....\.....\vloghmdd6q
...................................\....\.....\vlogmt58ag
...................................\....\.....\vlogn9hrit
...................................\....\.....\vlogq6v2ej
...................................\....\.....\vlogti66af
...................................\....\.....\vlogvj0kih
...................................\....\.....\vlogvs46v1
...................................\....\.....\vlogwjmwtz
...................................\....\.....\vlogx2wq4b
...................................\....\.....\vlogzb47mw
...................................\....\.....\vlogzj413a
...................................\....\.....\vlogzr38d5
...................................\....\.....\vlogzsb6vd
...................................\....\_info
...................................\....\_vmake
...................................\ALU.v
...................................\Branch_Data_Forwarding.v
...................................\Branch_Data_Forwarding.v.bak
...................................\Branch_pred.v
...................................\Controller.v
...................................\Controller.v.bak
...................................\data_mem.txt
...................................\EX_MEM.v
...................................\EX_MEM.v.bak
...................................\EX_MEM_DataForwarding.v
...................................\ID_EX.v
...................................\ID_EX.v.bak
...................................\IF_ID.v
...................................\InstMem.v
...................................\inst_mem.txt
...................................\MemData.v
...................................\MEM_WB.v
...................................\pc.v
...................................\pipeline.cr.mti
...................................\pipeline.mpf
...................................\Processor.v
...................................\Processor.v.bak
...................................\ProcessorTest.v
...................................\RegFile.v
...................................\RegFile.v.bak
...................................\tcl_stacktrace.txt
...................................\testDescription.txt
...................................\vsim.wlf