Random-number-generator-verilog Verilog code for a pseudo random number generator using line - source code download

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Random-number-generator-verilog

Classification:Hardware/embedded - VHDL Develop Development Tool:VHDL Sise:1.12 MB Upload time:2015/1/11 4:58:17 Uploader:juan93 Download Statistics:

Description

Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.

File list:
110445D_DSD_Individual
.....................\Code
.....................\....\lfsr.v
.....................\....\sseg.v
.....................\testbench
.....................\.........\lfsr_rng_test.v
.....................\ucf
.....................\...\lfsr_rng.ucf
.....................\110445D_individual report.pdf
.....................\13bit_lfsr.circ
.....................\13bit_lfsr.jpg

.....................\4bit_lfsr.JPG

.....................\netlist.JPG

.....................\RTL_3.png

.....................\schematic.pdf
.....................\Simulation.JPG

.....................\Simulation.wcfg
.....................\summary.JPG

.....................\tech1.png

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