pll(phase locked loop) is used to fix the circuit to particular frequency




File list:
bottom0level0detector.spc
header.sp
PFD.spc
pll(io).wdb
pll.spc
pll_power.wdb
pll_power_inout.wdb
pll_power_inoutzip.log
pll_power_inoutzip.out
pll_vi(withinput).wdb
pll_vi.wdb
Time and power.docx