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Frecuency-Divisor
  • Classification:Hardware/embedded - VHDL Develop
  • Development Tool:VHDL
  • Sise:129 KB
  • Upload time:2014/5/9 0:53:58
  • Uploader:jay641021
  • Download Statistics:
Description
This code Use the 50 Mhz clock of BASYS 2 FPGA to generate a frecuency divisor (choose the div value using FPGA Switches). The result is shown in two leds to compare, one have a frecency fixed (with out div ) and the secon led showm the div selected (by switches), working.




File list:
DivisorFrecuencia
................\ipcore_dir
................\iseconfig
................\.........\Divisor.xreport
................\.........\DivisorFrecuencia.projectmgr
................\xlnx_auto_0_xdb
................\...............\cst.xbcd
................\xst
................\...\dump.xst
................\...\........\Divisor.prj
................\...\........\...........\ngx
................\...\........\...........\...\notopt
................\...\........\...........\...\opt
................\...\projnav.tmp
................\...\work
................\...\....\vlg54
................\...\....\.....\_divisor.bin
................\...\....\vlg5B
................\...\....\.....\_multiplexor8a1.bin
................\...\....\vlg66
................\...\....\.....\_contador.bin
................\...\....\hdllib.ref
................\_ngo
................\....\netlist.lst
................\_xmsgs
................\......\bitgen.xmsgs
................\......\map.xmsgs
................\......\ngdbuild.xmsgs
................\......\par.xmsgs
................\......\pn_parser.xmsgs
................\......\trce.xmsgs
................\......\xst.xmsgs
................\Contador.bmm
................\Contador.v
................\divisor.bgn
................\divisor.bit
................\Divisor.bld
................\Divisor.cmd_log
................\divisor.drc
................\Divisor.lso
................\Divisor.ncd
................\Divisor.ngc
................\Divisor.ngd
................\Divisor.ngr
................\Divisor.pad
................\Divisor.par
................\Divisor.pcf
................\Divisor.prj
................\Divisor.ptwx
................\Divisor.stx
................\Divisor.syr
................\Divisor.twr
................\Divisor.twx
................\Divisor.unroutes
................\Divisor.ut
................\Divisor.v
................\Divisor.xpi
................\Divisor.xst
................\DivisorFrecuencia.gise
................\DivisorFrecuencia.xise
................\Divisor_bitgen.xwbt
................\Divisor_envsettings.html
................\Divisor_guide.ncd
................\Divisor_map.map
................\Divisor_map.mrp
................\Divisor_map.ncd
................\Divisor_map.ngm
................\Divisor_map.xrpt
................\Divisor_ngdbuild.xrpt
................\Divisor_pad.csv
................\Divisor_pad.txt
................\Divisor_par.xrpt
................\Divisor_summary.html
................\Divisor_summary.xml
................\Divisor_usage.xml
................\Divisor_utf.ucf
................\Divisor_xst.xrpt
................\Multiplexor8a1.v
................\usage_statistics_webtalk.html
................\webtalk.log
................\webtalk_pn.xml
Related source code
[Variable frecuency clk] - A simple frecuency generator , that allows you to generate 4 different frecuencys , depending of the variable op: "00", "01", "10" or "11"
[filtradofrecuencccial] - proceso de filtrado frecuencial en imagenes complete source code, has been tested.
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