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NERP_demo
  • Classification:Hardware/embedded - VHDL Develop
  • Development Tool:VHDL
  • Sise:44.0 KB
  • Upload time:2014/8/15 1:25:35
  • Uploader:pradipkumar0188
  • Download Statistics:
Description
VGA port programming for FPGA




File list:
NERP_demo
........\ipcore_dir
........\iseconfig
........\.........\NERP_demo.projectmgr
........\.........\NERP_demo_top.xreport
........\_xmsgs
........\clockdiv.v
........\NERP_demo.gise
........\NERP_demo.xise
........\nerp_demo_top.bit
........\NERP_demo_top.v
........\NERP_demo_top_bitgen.xwbt
........\NERP_demo_top_guide.ncd
........\NERP_demo_top_summary.html
........\Nexys2_1200General.ucf
........\segdisplay.v
........\vga640x480.v
Related source code
[WINNERP-calibration-data] - WINNER Channel calibration
[autotunerPID] - PID_TUNING Tune the parameters of a ISA PID regulator with some well defined auto tuning methods -PID_TUNING Tune the parameters of a ISA PID regulator with some well defined auto tuning methods
[DiagramDesignerPart4] - chart design code,using chart
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