verilog design of lut sr random number generator




File list:
lutsr
....\isim
....\....\file graph
....\....\work
....\....\....\rng_n1024_r32_t5_k32_s1c48
....\....\....\..........................\mingw
....\....\....\..........................\.....\rtl.obj
....\....\....\..........................\rtl.h
....\....\....\rng_n1024_r32_t5_k32_s1c48_sr
....\....\....\.............................\mingw
....\....\....\.............................\.....\rtl.obj
....\....\....\.............................\rtl.h
....\....\....\sub00
....\....\....\.....\vhpl00.vho
....\....\....\.....\vhpl01.vho
....\....\....\.....\vhpl02.vho
....\....\....\.....\vhpl03.vho
....\....\....\.....\vhpl04.vho
....\....\....\.....\vhpl05.vho
....\....\....\.....\vhpl06.vho
....\....\....\.....\vhpl07.vho
....\....\....\test
....\....\....\....\mingw
....\....\....\....\.....\testbench_arch.obj
....\....\....\....\testbench_arch.h
....\....\....\....\xsimtestbench_arch.cpp
....\....\....\test_rng_n1024_r32_t5_k32_s1c48
....\....\....\...............................\mingw
....\....\....\...............................\.....\behavior.obj
....\....\....\...............................\behavior.h
....\....\....\...............................\xsimbehavior.cpp
....\....\....\hdllib.ref
....\....\....\hdpdeps.ref
....\isim.tmp_save
....\.............\_1
....\xst
....\...\dump.xst
....\...\........\rng_n1024_r32_t5_k32_s1c48.prj
....\...\........\..............................\ngx
....\...\........\..............................\...\notopt
....\...\........\..............................\...\opt
....\...\........\..............................\ntrc.scr
....\...\projnav.tmp
....\...\work
....\...\....\sub00
....\...\....\.....\vhpl00.vho
....\...\....\.....\vhpl01.vho
....\...\....\.....\vhpl02.vho
....\...\....\.....\vhpl03.vho
....\...\....\hdllib.ref
....\...\....\hdpdeps.ref
....\_xmsgs
....\......\fuse.xmsgs
....\......\vhpcomp.xmsgs
....\......\xst.xmsgs
....\.lso
....\code.vhd
....\code_summary.html
....\isim.cmd
....\isim.hdlsourcefiles
....\isim.log
....\isimwavedata.xwv
....\jhyu.vhd
....\lutsr.ise
....\lutsr.ise_ISE_Backup
....\lutsr.ntrc_log
....\pepExtractor.prj
....\results.txt
....\rng_n1024_r32_t5_k32_s1c48.cmd_log
....\rng_n1024_r32_t5_k32_s1c48.lso
....\rng_n1024_r32_t5_k32_s1c48.ngc
....\rng_n1024_r32_t5_k32_s1c48.ngr
....\rng_n1024_r32_t5_k32_s1c48.prj
....\rng_n1024_r32_t5_k32_s1c48.stx
....\rng_n1024_r32_t5_k32_s1c48.syr
....\rng_n1024_r32_t5_k32_s1c48.xst
....\rng_n1024_r32_t5_k32_s1c48_SR.prj
....\rng_n1024_r32_t5_k32_s1c48_SR.stx
....\rng_n1024_r32_t5_k32_s1c48_SR.xst
....\rng_n1024_r32_t5_k32_s1c48_SR_vhdl.prj
....\rng_n1024_r32_t5_k32_s1c48_summary.html
....\rng_n1024_r32_t5_k32_s1c48_vhdl.prj
....\test.ant
....\test.jhd
....\test.tbw
....\test.vhw
....\test.xwv
....\test.xwv_bak
....\test1.xwv
....\test1.xwv_bak
....\test12.xwv
....\test12.xwv_bak
....\test12_bencher.prj
....\test1_bencher.prj
....\test_beh.prj
....\test_bencher.prj
....\test_isim_beh.exe
....\test_rng_n1024_r32_t5_k32_s1c48_beh.prj
....\test_rng_n1024_r32_t5_k32_s1c48_isim_beh.exe
....\xilinxsim.ini