XAPP585 serdes_1_to_7 and serdes_7_to_1 data




File list:
XAPP_585
.......\ucf
.......\...\top5x2_7to1_ddr_rx.ucf
.......\...\top5x2_7to1_ddr_tx.ucf
.......\...\top5x2_7to1_sdr_rx.ucf
.......\...\top5x2_7to1_sdr_tx.ucf
.......\Verilog_macros
.......\..............\clock_generator_pll_7_to_1_diff_ddr.v
.......\..............\clock_generator_pll_7_to_1_diff_sdr.v
.......\..............\gearbox_4_to_7.v
.......\..............\n_x_serdes_1_to_7_mmcm_idelay_ddr.v
.......\..............\n_x_serdes_1_to_7_mmcm_idelay_sdr.v
.......\..............\n_x_serdes_7_to_1_diff_ddr.v
.......\..............\n_x_serdes_7_to_1_diff_sdr.v
.......\..............\serdes_1_to_7_mmcm_idelay_ddr.v
.......\..............\serdes_1_to_7_mmcm_idelay_sdr.v
.......\..............\serdes_1_to_7_slave_idelay_ddr.v
.......\..............\serdes_1_to_7_slave_idelay_sdr.v
.......\..............\serdes_7_to_1_diff_ddr.v
.......\..............\serdes_7_to_1_diff_sdr.v
.......\Verilog_testbench
.......\.................\tb_top5x2_7to1_ddr.v
.......\.................\tb_top5x2_7to1_sdr.v
.......\Verilog_top_level_examples
.......\..........................\top5x2_7to1_ddr_rx.v
.......\..........................\top5x2_7to1_ddr_tx.v
.......\..........................\top5x2_7to1_sdr_rx.v
.......\..........................\top5x2_7to1_sdr_tx.v
.......\VHDL_macros
.......\...........\clock_generator_pll_7_to_1_diff_ddr.vhd
.......\...........\clock_generator_pll_7_to_1_diff_sdr.vhd
.......\...........\gearbox_4_to_7.vhd
.......\...........\n_x_serdes_1_to_7_mmcm_idelay_ddr.vhd
.......\...........\n_x_serdes_1_to_7_mmcm_idelay_sdr.vhd
.......\...........\n_x_serdes_7_to_1_diff_ddr.vhd
.......\...........\n_x_serdes_7_to_1_diff_sdr.vhd
.......\...........\serdes_1_to_7_mmcm_idelay_ddr.vhd
.......\...........\serdes_1_to_7_mmcm_idelay_sdr.vhd
.......\...........\serdes_1_to_7_slave_idelay_ddr.vhd
.......\...........\serdes_1_to_7_slave_idelay_sdr.vhd
.......\...........\serdes_7_to_1_diff_ddr.vhd
.......\...........\serdes_7_to_1_diff_sdr.vhd
.......\VHDL_testbench
.......\..............\tb_top5x2_7to1_ddr.vhd
.......\..............\tb_top5x2_7to1_sdr.vhd
.......\VHDL_top_level_examples
.......\.......................\top5x2_7to1_ddr_rx.vhd
.......\.......................\top5x2_7to1_ddr_tx.vhd
.......\.......................\top5x2_7to1_sdr_rx.vhd
.......\.......................\top5x2_7to1_sdr_tx.vhd
.......\readme.txt
.......\xapp585-lvds-source-synch-serdes-clock-multiplication.pdf
.......\xapp585_ Uncertainties_ tool_ 1.1.xlsx