ALU fool test bench of ALU aritmetic logic unit written in VHDL - source code download

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ALU

Classification:Hardware/embedded - VHDL Develop Development Tool:VHDL Sise:595 KB Upload time:2014/7/28 3:23:26 Uploader:cqbmax444 Download Statistics:

Description

fool test bench of ALU aritmetic logic unit written in VHDL language

File list:
db
.\ALU.(0).cnf.cdb
.\ALU.(0).cnf.hdb
.\ALU.amm.cdb
.\ALU.asm.qmsg
.\ALU.asm.rdb
.\ALU.asm_labs.ddb
.\ALU.cbx.xml
.\ALU.cmp.bpm
.\ALU.cmp.cdb
.\ALU.cmp.hdb
.\ALU.cmp.kpt
.\ALU.cmp.logdb
.\ALU.cmp.rdb
.\ALU.cmp0.ddb
.\ALU.cmp1.ddb
.\ALU.cmp_merge.kpt
.\ALU.db_info
.\ALU.eda.qmsg
.\ALU.fit.qmsg
.\ALU.hier_info
.\ALU.hif
.\ALU.idb.cdb
.\ALU.lpc.html
.\ALU.lpc.rdb
.\ALU.lpc.txt
.\ALU.map.bpm
.\ALU.map.cdb
.\ALU.map.hdb
.\ALU.map.kpt
.\ALU.map.logdb
.\ALU.map.qmsg
.\ALU.map_bb.cdb
.\ALU.map_bb.hdb
.\ALU.map_bb.logdb
.\ALU.pre_map.cdb
.\ALU.pre_map.hdb
.\ALU.rtlv.hdb
.\ALU.rtlv_sg.cdb
.\ALU.rtlv_sg_swap.cdb
.\ALU.sgdiff.cdb
.\ALU.sgdiff.hdb
.\ALU.sld_design_entry.sci
.\ALU.sld_design_entry_dsc.sci
.\ALU.smart_action.txt
.\ALU.sta.qmsg
.\ALU.sta.rdb
.\ALU.sta_cmp.6_slow.tdb
.\ALU.syn_hier_info
.\ALU.tis_db_list.ddb
.\ALU.tmw_info
.\logic_util_heursitic.dat
incremental_db
.............\compiled_partitions
.............\...................\ALU.db_info
.............\...................\ALU.root_partition.cmp.cdb
.............\...................\ALU.root_partition.cmp.dfp
.............\...................\ALU.root_partition.cmp.hdb
.............\...................\ALU.root_partition.cmp.kpt
.............\...................\ALU.root_partition.cmp.logdb
.............\...................\ALU.root_partition.cmp.rcfdb
.............\...................\ALU.root_partition.map.cdb
.............\...................\ALU.root_partition.map.dpi
.............\...................\ALU.root_partition.map.hbdb.cdb
.............\...................\ALU.root_partition.map.hbdb.hb_info
.............\...................\ALU.root_partition.map.hbdb.hdb
.............\...................\ALU.root_partition.map.hbdb.sig
.............\...................\ALU.root_partition.map.hdb
.............\...................\ALU.root_partition.map.kpt
.............\README
simulation
.........\modelsim
.........\........\rtl_work
.........\........\........\alu
.........\........\........\...\behave.dat
.........\........\........\...\behave.dbs
.........\........\........\...\behave.prw
.........\........\........\...\behave.psm
.........\........\........\...\_primary.dat
.........\........\........\...\_primary.dbs
.........\........\........\alu_test_bench
.........\........\........\..............\stimulus.dat
.........\........\........\..............\stimulus.dbs
.........\........\........\..............\stimulus.prw
.........\........\........\..............\stimulus.psm
.........\........\........\..............\_primary.dat
.........\........\........\..............\_primary.dbs
.........\........\........\_temp
.........\........\........\_info
.........\........\........\_vmake
.........\........\ALU.sft
.........\........\ALU.vho
.........\........\ALU_fast.vho
.........\........\ALU_modelsim.xrf
.........\........\ALU_run_msim_rtl_vhdl.do
.........\........\ALU_run_msim_rtl_vhdl.do.bak
.........\........\ALU_run_msim_rtl_vhdl.do.bak1
.........\........\ALU_run_msim_rtl_vhdl.do.bak2
.........\........\ALU_vhd.sdo
.........\........\ALU_vhd_fast.sdo
.........\........\modelsim.ini
.........\........\msim_transcript
.........\........\vsim.wlf
ALU.asm.rpt
alu.doc
ALU.done
ALU.eda.rpt
ALU.fit.rpt
ALU.fit.smsg
ALU.fit.summary
ALU.flow.rpt
ALU.map.rpt
ALU.map.summary
ALU.pin
ALU.pof
ALU.qpf
ALU.qsf
ALU.sof
ALU.sta.rpt
ALU.sta.summary
ALU.vhd
alu.vhd.bak
ALU_description.txt
ALU_nativelink_simulation.rpt
ALU_test_bench.vhd
ALU_test_bench.vhd.bak

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