Full Adder 4bit, using VHDL, Quartus Altera




File list:
Fulladder4bit
............\db
............\..\full4bit.(0).cnf.cdb
............\..\full4bit.(0).cnf.hdb
............\..\full4bit.cbx.xml
............\..\full4bit.cmp.rdb
............\..\full4bit.db_info
............\..\full4bit.hif
............\..\full4bit.ipinfo
............\..\full4bit.map.qmsg
............\..\full4bit.map.rdb
............\..\full4bit.map_bb.hdb
............\..\full4bit.pre_map.hdb
............\..\full4bit.qns
............\..\full4bit.sas
............\..\full4bit.sld_design_entry.sci
............\..\full4bit.smart_action.txt
............\..\full4bit.tis_db_list.ddb
............\..\logic_util_heursitic.dat
............\..\prev_cmp_full4bit.qmsg
............\output_files
............\............\full4bit.flow.rpt
............\............\full4bit.map.rpt
............\............\full4bit.map.summary
............\full4bit.bdf
............\full4bit.qpf
............\full4bit.qsf
............\full4bit.qws