carry ripple adder and 7segment with vhdl.i hopr people who use this project di not just cheat it




File list:
VHDL_IUST_Fall2012_90611046
..........................\1-adder4 with testbench.txt
..........................\2-ripple_carry4 with testbench.txt
..........................\3-carry_select4 with testbench.txt
..........................\4-ripple_carry n bit with testbench.txt
..........................\5-carry_select n bit with testbench.txt
..........................\6-7seg decoder with testbench.txt
..........................\7-display sum on 7seg with testbench.txt
..........................\p1.doc