This project is designed to VGA Vhdl language.




File list:
vga_ easy
........\n
........\.\ipcore_dir
........\.\iseconfig
........\.\.........\n.projectmgr
........\.\.........\top.xreport
........\.\.........\VHDL_VGA.xreport
........\.\n_xdb
........\.\.....\tmp
........\.\.....\...\ise
........\.\.....\...\...\__OBJSTORE__
........\.\.....\...\...\............\Autonym
........\.\.....\...\...\............\common
........\.\.....\...\...\............\HierarchicalDesign
........\.\.....\...\...\............\..................\HDProject
........\.\.....\...\...\............\..................\.........\HDProject
........\.\.....\...\...\............\..................\.........\HDProject_StrTbl
........\.\.....\...\...\............\..................\__stored_object_table__
........\.\.....\...\...\............\PnAutoRun
........\.\.....\...\...\............\.........\Scripts
........\.\.....\...\...\............\.........\.......\RunOnce_tcl
........\.\.....\...\...\............\.........\.......\RunOnce_tcl_StrTbl
........\.\.....\...\...\............\ProjectNavigator
........\.\.....\...\...\............\................\dpm_project_main
........\.\.....\...\...\............\................\................\dpm_project_main
........\.\.....\...\...\............\................\................\dpm_project_main_StrTbl
........\.\.....\...\...\............\ProjectNavigator11
........\.\.....\...\...\............\ProjectNavigatorGui
........\.\.....\...\...\............\...................\CViewSelector
........\.\.....\...\...\............\...................\CViewSelector_StrTbl
........\.\.....\...\...\............\...................\File-SynthesisOnly
........\.\.....\...\...\............\...................\File-SynthesisOnly_StrTbl
........\.\.....\...\...\............\...................\Library-SynthesisOnly
........\.\.....\...\...\............\...................\Library-SynthesisOnly_StrTbl
........\.\.....\...\...\............\...................\Process-SynthesisOnly-DESUT_SCHEMATIC
........\.\.....\...\...\............\...................\Process-SynthesisOnly-DESUT_SCHEMATIC_StrTbl
........\.\.....\...\...\............\...................\Source-SynthesisOnly-AutoCompile
........\.\.....\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
........\.\.....\...\...\............\xreport
........\.\.....\...\...\............\.......\Gc_RvReportViewer-Current-Module
........\.\.....\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
........\.\.....\...\...\............\.......\Gc_RvReportViewer-Module-Data-top
........\.\.....\...\...\............\.......\Gc_RvReportViewer-Module-Data-top_StrTbl
........\.\.....\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
........\.\.....\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
........\.\.....\...\...\............\_ProjRepoInternal_
........\.\.....\...\...\__REGISTRY__
........\.\.....\...\...\............\Autonym
........\.\.....\...\...\............\.......\regkeys
........\.\.....\...\...\............\bitgen
........\.\.....\...\...\............\......\regkeys
........\.\.....\...\...\............\bitinit
........\.\.....\...\...\............\.......\regkeys
........\.\.....\...\...\............\common
........\.\.....\...\...\............\......\regkeys
........\.\.....\...\...\............\cpldfit
........\.\.....\...\...\............\.......\regkeys
........\.\.....\...\...\............\dumpngdio
........\.\.....\...\...\............\.........\regkeys
........\.\.....\...\...\............\fuse
........\.\.....\...\...\............\....\regkeys
........\.\.....\...\...\............\HierarchicalDesign
........\.\.....\...\...\............\..................\HDProject
........\.\.....\...\...\............\..................\.........\regkeys
........\.\.....\...\...\............\hprep6
........\.\.....\...\...\............\......\regkeys
........\.\.....\...\...\............\idem
........\.\.....\...\...\............\....\regkeys
........\.\.....\...\...\............\libgen
........\.\.....\...\...\............\......\regkeys
........\.\.....\...\...\............\map
........\.\.....\...\...\............\...\regkeys
........\.\.....\...\...\............\netgen
........\.\.....\...\...\............\......\regkeys
........\.\.....\...\...\............\ngc2edif
........\.\.....\...\...\............\........\regkeys
........\.\.....\...\...\............\ngcbuild
........\.\.....\...\...\............\........\regkeys
........\.\.....\...\...\............\ngdbuild
........\.\.....\...\...\............\........\regkeys
........\.\.....\...\...\............\par
........\.\.....\...\...\............\...\regkeys
........\.\.....\...\...\............\platgen
........\.\.....\...\...\............\.......\regkeys
........\.\.....\...\...\............\ProjectNavigator
........\.\.....\...\...\............\................\regkeys
........\.\.....\...\...\............\ProjectNavigator11
........\.\.....\...\...\............\..................\regkeys
........\.\.....\...\...\............\ProjectNavigatorGui
........\.\.....\...\...\............\...................\regkeys
........\.\.....\...\...\............\runner
........\.\.....\...\...\............\......\regkeys
........\.\.....\...\...\............\simgen
........\.\.....\...\...\............\......\regkeys
........\.\.....\...\...\............\taengine
........\.\.....\...\...\............\........\regkeys
........\.\.....\...\...\............\trce
........\.\.....\...\...\............\....\regkeys
........\.\.....\...\...\............\tsim
........\.\.....\...\...\............\....\regkeys
........\.\.....\...\...\............\vhpcomp
........\.\.....\...\...\............\.......\regkeys
........\.\.....\...\...\............\vlogcomp
........\.\.....\...\...\............\........\regkeys
........\.\.....\...\...\............\xpwr
........\.\.....\...\...\............\....\regkeys
........\.\.....\...\...\............\xreport
........\.\.....\...\...\............\.......\regkeys
........\.\.....\...\...\............\XSLTProcess
........\.\.....\...\...\............\...........\regkeys
........\.\.....\...\...\............\xst
........\.\.....\...\...\............\...\regkeys
........\.\.....\...\...\............\_ProjRepoInternal_
........\.\.....\...\...\............\..................\regkeys
........\.\.....\...\...\version
........\.\.....\...\ise.lock
........\.\.....\cst.xbcd
........\.\patmp
........\.\.....\n.data
........\.\.....\......\da
........\.\.....\......\..\elab.xml
........\.\.....\......\floorplans
........\.\.....\......\..........\floorplan_1
........\.\.....\......\..........\...........\iseloc.xml
........\.\.....\......\..........\...........\pfi.xml
........\.\.....\......\..........\...........\pfp.xml
........\.\.....\......\..........\...........\userCols.xml
........\.\.....\......\netlists
........\.\.....\......\........\netlist_1
........\.\.....\......\........\.........\nlh.xml
........\.\.....\......\........\.........\top.edn
........\.\.....\n.ppr
........\.\xlnx_auto_0_xdb
........\.\...............\cst.xbcd
........\.\xst
........\.\...\dump.xst
........\.\...\........\top.prj
........\.\...\........\.......\ngx
........\.\...\........\.......\...\notopt
........\.\...\........\.......\...\opt
........\.\...\........\VHDL_VGA.prj
........\.\...\........\............\ngx
........\.\...\........\............\...\notopt
........\.\...\........\............\...\opt
........\.\...\file graph
........\.\...\projnav.tmp
........\.\...\work
........\.\...\....\sub00
........\.\...\....\.....\vhpl00.vho
........\.\...\....\.....\vhpl01.vho
........\.\...\....\.....\vhpl02.vho
........\.\...\....\.....\vhpl03.vho
........\.\...\....\hdllib.ref
........\.\...\....\hdpdeps.ref
........\.\_ngo
........\.\....\netlist.lst
........\.\_xmsgs
........\.\......\bitgen.xmsgs
........\.\......\map.xmsgs
........\.\......\ngdbuild.xmsgs
........\.\......\par.xmsgs
........\.\......\pn_parser.xmsgs
........\.\......\trce.xmsgs
........\.\......\xst.xmsgs
........\.\device_usage_statistics.html
........\.\gt.vhd
........\.\gt.vhdPreview
........\.\gt_summary.html
........\.\lcd_driver_summary.html
........\.\main_summary.html
........\.\n.gise
........\.\n.ise
........\.\n.ntrc_log
........\.\n.xise
........\.\n_pa.log
........\.\n_pa_ports.v
........\.\output.txt
........\.\pa.fromHdl.tcl
........\.\pa.fromHdlPorts.tcl
........\.\pac.ucf
........\.\pepExtractor.prj
........\.\planAhead.jou
........\.\planAhead.log
........\.\sch2HdlBatchFile
........\.\top.bgn
........\.\top.bit
........\.\top.bld
........\.\top.cmd_log
........\.\top.drc
........\.\top.jhd
........\.\top.lso
........\.\top.ncd
........\.\top.ngc
........\.\top.ngd
........\.\top.ngr
........\.\top.pad
........\.\top.par
........\.\top.pcf
........\.\top.prj
........\.\top.ptwx
........\.\top.sch
........\.\top.stx
........\.\top.syr
........\.\top.twr
........\.\top.twx
........\.\top.unroutes
........\.\top.ut
........\.\top.vhf
........\.\top.xpi
........\.\top.xst
........\.\top_bitgen.xwbt
........\.\top_envsettings.html
........\.\top_guide.ncd
........\.\top_map.map
........\.\top_map.mrp
........\.\top_map.ncd
........\.\top_map.ngm
........\.\top_map.xrpt
........\.\top_ngdbuild.xrpt
........\.\top_pad.csv
........\.\top_pad.txt
........\.\top_par.xrpt
........\.\top_summary.html
........\.\top_summary.xml
........\.\top_usage.xml
........\.\top_vhdl.prj
........\.\top_xst.xrpt
........\.\Untitled2.cfi
........\.\Untitled2.mcs
........\.\Untitled2.prm
........\.\Untitled2.sig
........\.\usage_statistics_webtalk.html
........\.\vhdl_vga.bgn
........\.\vhdl_vga.bit
........\.\VHDL_VGA.bld
........\.\VHDL_VGA.cmd_log
........\.\vhdl_vga.drc
........\.\VHDL_VGA.lso
........\.\VHDL_VGA.ncd
........\.\VHDL_VGA.ngc
........\.\VHDL_VGA.ngd
........\.\VHDL_VGA.ngr
........\.\VHDL_VGA.pad
........\.\VHDL_VGA.par
........\.\VHDL_VGA.pcf
........\.\VHDL_VGA.prj
........\.\VHDL_VGA.ptwx
........\.\VHDL_VGA.spl
........\.\VHDL_VGA.stx
........\.\VHDL_VGA.sym
........\.\VHDL_VGA.syr
........\.\VHDL_VGA.twr
........\.\VHDL_VGA.twx
........\.\VHDL_VGA.unroutes
........\.\VHDL_VGA.ut
........\.\VHDL_VGA.vhi
........\.\VHDL_VGA.xpi
........\.\VHDL_VGA.xst
........\.\VHDL_VGA_bitgen.xwbt
........\.\VHDL_VGA_envsettings.html
........\.\VHDL_VGA_guide.ncd
........\.\VHDL_VGA_map.map
........\.\VHDL_VGA_map.mrp
........\.\VHDL_VGA_map.ncd
........\.\VHDL_VGA_map.ngm
........\.\VHDL_VGA_map.xrpt
........\.\VHDL_VGA_pad.csv
........\.\VHDL_VGA_pad.txt
........\.\VHDL_VGA_par.xrpt
........\.\VHDL_VGA_prev_built.ngd
........\.\VHDL_VGA_summary.html
........\.\VHDL_VGA_summary.xml
........\.\VHDL_VGA_usage.xml
........\.\VHDL_VGA_vhdl.prj
........\.\VHDL_VGA_xst.xrpt
........\.\webtalk.log
........\.\webtalk_pn.xml
........\.\_impact.cmd
........\.\_impact.log
........\output.txt
........\Untitled.cfi
........\Untitled.mcs
........\Untitled.prm
........\Untitled.sig