dvi encoder and decoder for fpga




File list:
dvi code verilog
...............\model
...............\.....\CY7C1338G_FT.v
...............\.....\CY7C1338G_FT_.v
...............\.....\dvi_patten_gen.v
...............\.....\mcu_stimulus.vhd
...............\.....\patten_gen.v
...............\.....\patten_gen_with_btn.v
...............\.....\patten_sel.v
...............\.....\swap_ctrl.v
...............\.....\vga2.vhd
...............\.....\VGA_Controller.v
...............\.....\VGA_Param.h
...............\.....\vssver.scc
...............\rtl
...............\...\common
...............\...\......\debnce.v
...............\...\......\hdclrbar.v
...............\...\......\synchro.v
...............\...\......\timing.v
...............\...\......\vssver.scc
...............\...\core_gen
...............\...\........\tmp
...............\...\........\...\_cg
...............\...\........\coregen.cgp
...............\...\........\vssver.scc
...............\...\dvi_ip
...............\...\......\core
...............\...\......\....\dvi_tx_fifo.coe
...............\...\......\....\dvi_tx_fifo.mif
...............\...\......\....\dvi_tx_fifo.ngc
...............\...\......\....\dvi_tx_fifo.v
...............\...\......\....\dvi_tx_fifo.veo
...............\...\......\....\dvi_tx_fifo.xco
...............\...\......\....\dvi_tx_fifo_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt
...............\...\......\....\dvi_tx_fifo_flist.txt
...............\...\......\....\dvi_tx_fifo_readme.txt
...............\...\......\....\dvi_tx_fifo_xmdf.tcl
...............\...\......\....\inputbuffer.ngc
...............\...\......\....\inputbuffer.vhd
...............\...\......\....\inputbuffer.vho
...............\...\......\....\inputbuffer.xco
...............\...\......\....\inputbuffer_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt
...............\...\......\....\inputbuffer_flist.txt
...............\...\......\....\inputbuffer_readme.txt
...............\...\......\....\inputbuffer_xmdf.tcl
...............\...\......\chnlbond.v
...............\...\......\dcminit.v
...............\...\......\decode.v
...............\...\......\DRAM16XN.v
...............\...\......\dvi_decoder.v
...............\...\......\dvi_encoder.v
...............\...\......\dvi_ip.v
...............\...\......\encode.v
...............\...\......\patten_gen.v
...............\...\......\phsaligner.v
...............\...\......\resync_1024fifo.v
...............\...\......\resync_part_new.vhd
...............\...\......\serdes_4b_10to1_fifo.v
...............\...\......\sync_monitor.v
...............\...\......\tmds_1c_1to10.v
...............\...\......\vssver.scc
...............\...\......\watch_dog.v
...............\...\new_resync
...............\...\..........\inputbuffer.ngc
...............\...\..........\inputbuffer.vhd
...............\...\..........\inputbuffer.vho
...............\...\..........\inputbuffer.xco
...............\...\..........\inputbuffer_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt
...............\...\..........\inputbuffer_flist.txt
...............\...\..........\inputbuffer_readme.txt
...............\...\..........\inputbuffer_xmdf.tcl
...............\...\..........\resync_part_new.vhd
...............\...\clk_ctrl.v
...............\...\ctrl_main.ucf
...............\...\ctrl_main.v
...............\...\dvi_ctrl.v
...............\...\reset_gen.v
...............\...\trig_cnt.v
...............\...\up_registers.v
...............\...\vsync_stu_led.v
...............\sim
...............\...\clean_project.bat
...............\...\dvi_demo.mpf
...............\...\dvi_tx_fifo.mif
...............\...\gamma_data.TXT
...............\...\glbl.v
...............\...\glbl_set.h
...............\...\reg_data.TXT
...............\...\reg_dataa.TXT
...............\...\restart
...............\...\s3a_logo.v
...............\...\sim.td
...............\...\sram_data.TXT
...............\...\tb_dvi_demo.v
...............\...\vlog.opt
...............\...\vssver.scc
...............\syn
...............\...\div_test.prj
...............\...\glbl_set.h
...............\version.txt