A 5 stage pipeline CPU written in verilog codes




File list:
proc_pipeline
............\alu.v
............\alu_adder_16.v
............\alu_and_16.v
............\alu_cla_4.v
............\alu_cla_GP.v
............\alu_ext.v
............\alu_or_16.v
............\alu_xor_16.v
............\clkrst.v
............\ctrl_unit.v
............\data_mem2c.v
............\decoder_3to8.v
............\dff.v
............\dff_en.v
............\execution.v
............\forwarding_unit.v
............\hazard_detection.v
............\inst_decode.v
............\inst_fetch.v
............\inst_mem2c.v
............\mem.v
............\memory2c.v
............\mux_2to1_16bit.v
............\mux_2to1_1bit.v
............\mux_4to1_16bit.v
............\mux_4to1_1bit.v
............\mux_4to1_3bit.v
............\mux_8to1_16bit.v
............\mux_8to1_1bit.v
............\nand2.v
............\not1.v
............\pc_add_2.v
............\pc_add_2_high.v
............\pc_add_2_low.v
............\pc_add_jump.v
............\pc_reg.v
............\proc.v
............\proc_hier.v
............\proc_hier_pbench.v
............\README.txt
............\register_16bit.v
............\reg_EXE_MEM.v
............\reg_ID_EXE.v
............\reg_IF_ID.v
............\reg_MEM_WB.v
............\rf.v
............\rf_bypass.v
............\rs_process.v
............\shifter.v
............\shift_L_1.v
............\shift_L_2.v
............\shift_L_4.v
............\shift_L_8.v
............\shift_L_rotate_1.v
............\shift_L_rotate_2.v
............\shift_L_rotate_4.v
............\shift_L_rotate_8.v
............\shift_R_logic_1.v
............\shift_R_logic_2.v
............\shift_R_logic_4.v
............\shift_R_logic_8.v
............\shift_R_rotate_1.v
............\shift_R_rotate_2.v
............\shift_R_rotate_4.v
............\shift_R_rotate_8.v
............\sign_ext_11.v
............\sign_ext_5.v
............\sign_ext_8.v
............\write_back.v
............\zero_ext_5.v