A RISC processor written in verilog codes.




File list:
risc 4-way lru processor verilog
...............................\acc.v
...............................\alu.v
...............................\bus_arbiter.v
...............................\cmd_ack.v
...............................\cmd_decoder.v
...............................\cmd_detector.v
...............................\cmd_generator.v
...............................\cmd_internal_reg.v
...............................\command_if.v
...............................\control.v
...............................\data_cache_way0.v
...............................\data_cache_way1.v
...............................\data_cache_way2.v
...............................\data_cache_way3.v
...............................\data_in_reg.v
...............................\data_port.v
...............................\dma_cntrl.v
...............................\dma_fifo.v
...............................\dma_internal_reg.v
...............................\flash_ctrl.v
...............................\fsm.v
...............................\instruction_cache_way0.v
...............................\instruction_cache_way1.v
...............................\instruction_cache_way2.v
...............................\instruction_cache_way3.v
...............................\ir.v
...............................\k9f1g08u0m.v
...............................\lru_data_cache.v
...............................\lru_instruction_cache.v
...............................\mem.v
...............................\mux12.v
...............................\mux16.v
...............................\oe_generator.v
...............................\parameter.v
...............................\pc.v
...............................\ras_cas_delay.v
...............................\REadme
...............................\REadme~
...............................\ref_ack.v
...............................\ref_timer.v
...............................\risc.v
...............................\sdramctrl_rtl.v
...............................\sdram_cntrl.v
...............................\sdram_mux.v
...............................\sdram_port.v
...............................\soc.v
...............................\timer.v
...............................\uart.v
...............................\uart.v~