FSM source–Next state calculation–Output calculation–State transition




File list:
db
.\logic_util_heursitic.dat
.\part1.(0).cnf.cdb
.\part1.(0).cnf.hdb
.\part1.(1).cnf.cdb
.\part1.(1).cnf.hdb
.\part1.asm.qmsg
.\part1.asm.rdb
.\part1.asm_labs.ddb
.\part1.cbx.xml
.\part1.cmp.bpm
.\part1.cmp.cdb
.\part1.cmp.hdb
.\part1.cmp.idb
.\part1.cmp.kpt
.\part1.cmp.logdb
.\part1.cmp.rdb
.\part1.cmp0.ddb
.\part1.cmp1.ddb
.\part1.cmp_merge.kpt
.\part1.db_info
.\part1.eda.qmsg
.\part1.fit.qmsg
.\part1.hier_info
.\part1.hif
.\part1.ipinfo
.\part1.lpc.html
.\part1.lpc.rdb
.\part1.lpc.txt
.\part1.map.bpm
.\part1.map.cdb
.\part1.map.hdb
.\part1.map.kpt
.\part1.map.logdb
.\part1.map.qmsg
.\part1.map.rdb
.\part1.map_bb.cdb
.\part1.map_bb.hdb
.\part1.map_bb.logdb
.\part1.pplq.rdb
.\part1.pre_map.cdb
.\part1.pre_map.hdb
.\part1.qns
.\part1.root_partition.map.reg_db.cdb
.\part1.routing.rdb
.\part1.rtlv.hdb
.\part1.rtlv_sg.cdb
.\part1.rtlv_sg_swap.cdb
.\part1.sas
.\part1.sgdiff.cdb
.\part1.sgdiff.hdb
.\part1.sld_design_entry.sci
.\part1.sld_design_entry_dsc.sci
.\part1.smart_action.txt
.\part1.sta.qmsg
.\part1.sta.rdb
.\part1.sta_cmp.6_slow.tdb
.\part1.syn_hier_info
.\part1.tis_db_list.ddb
.\part1.tmw_info
.\part1.vpr.ammdb
.\prev_cmp_part1.qmsg
incremental_db
.............\compiled_partitions
.............\...................\part1.db_info
.............\...................\part1.root_partition.cmp.ammdb
.............\...................\part1.root_partition.cmp.cdb
.............\...................\part1.root_partition.cmp.dfp
.............\...................\part1.root_partition.cmp.hdb
.............\...................\part1.root_partition.cmp.kpt
.............\...................\part1.root_partition.cmp.logdb
.............\...................\part1.root_partition.cmp.rcfdb
.............\...................\part1.root_partition.map.cdb
.............\...................\part1.root_partition.map.dpi
.............\...................\part1.root_partition.map.hbdb.cdb
.............\...................\part1.root_partition.map.hbdb.hb_info
.............\...................\part1.root_partition.map.hbdb.hdb
.............\...................\part1.root_partition.map.hbdb.sig
.............\...................\part1.root_partition.map.hdb
.............\...................\part1.root_partition.map.kpt
.............\README
output_files
...........\part1.asm.rpt
...........\part1.done
...........\part1.eda.rpt
...........\part1.fit.rpt
...........\part1.fit.smsg
...........\part1.fit.summary
...........\part1.flow.rpt
...........\part1.jdi
...........\part1.map.rpt
...........\part1.map.summary
...........\part1.pin
...........\part1.pof
...........\part1.sof
...........\part1.sta.rpt
...........\part1.sta.summary
simulation
.........\modelsim
.........\........\gate_work
.........\........\.........\@testbench
.........\........\.........\..........\verilog.prw
.........\........\.........\..........\verilog.psm
.........\........\.........\..........\_primary.dat
.........\........\.........\..........\_primary.dbs
.........\........\.........\..........\_primary.vhd
.........\........\.........\part1
.........\........\.........\.....\verilog.prw
.........\........\.........\.....\verilog.psm
.........\........\.........\.....\_primary.dat
.........\........\.........\.....\_primary.dbs
.........\........\.........\.....\_primary.vhd
.........\........\.........\_temp
.........\........\.........\_info
.........\........\.........\_vmake
.........\........\rtl_work
.........\........\........\@testbench
.........\........\........\..........\verilog.prw
.........\........\........\..........\verilog.psm
.........\........\........\..........\_primary.dat
.........\........\........\..........\_primary.dbs
.........\........\........\..........\_primary.vhd
.........\........\........\part1
.........\........\........\.....\verilog.prw
.........\........\........\.....\verilog.psm
.........\........\........\.....\_primary.dat
.........\........\........\.....\_primary.dbs
.........\........\........\.....\_primary.vhd
.........\........\........\seg
.........\........\........\...\verilog.prw
.........\........\........\...\verilog.psm
.........\........\........\...\_primary.dat
.........\........\........\...\_primary.dbs
.........\........\........\...\_primary.vhd
.........\........\........\_temp
.........\........\........\_info
.........\........\........\_vmake
.........\........\modelsim.ini
.........\........\msim_transcript
.........\........\part1.sft
.........\........\part1.vo
.........\........\part1_fast.vo
.........\........\part1_modelsim.xrf
.........\........\part1_run_msim_gate_verilog.do
.........\........\part1_run_msim_rtl_verilog.do
.........\........\part1_run_msim_rtl_verilog.do.bak
.........\........\part1_run_msim_rtl_verilog.do.bak1
.........\........\part1_run_msim_rtl_verilog.do.bak10
.........\........\part1_run_msim_rtl_verilog.do.bak11
.........\........\part1_run_msim_rtl_verilog.do.bak2
.........\........\part1_run_msim_rtl_verilog.do.bak3
.........\........\part1_run_msim_rtl_verilog.do.bak4
.........\........\part1_run_msim_rtl_verilog.do.bak5
.........\........\part1_run_msim_rtl_verilog.do.bak6
.........\........\part1_run_msim_rtl_verilog.do.bak7
.........\........\part1_run_msim_rtl_verilog.do.bak8
.........\........\part1_run_msim_rtl_verilog.do.bak9
.........\........\part1_v.sdo
.........\........\part1_v.sdo_typ.csd
.........\........\part1_v_fast.sdo
.........\........\vsim.wlf
part1.jdi
part1.qpf
part1.qsf
part1.qws
part1.v
part1.v.bak
part1_assignment_defaults.qdf
part1_nativelink_simulation.rpt
Testbench.v
Testbench.v.bak