this file was given as a VHDL programme




File list:
Devoir
.....\Modelsim
.....\........\work
.....\........\....\montre_num
.....\........\....\..........\rtl.dat
.....\........\....\..........\rtl.dbs
.....\........\....\..........\_primary.dat
.....\........\....\..........\_primary.dbs
.....\........\....\montre_tb
.....\........\....\.........\arch_tb.dat
.....\........\....\.........\arch_tb.dbs
.....\........\....\.........\_primary.dat
.....\........\....\.........\_primary.dbs
.....\........\....\_opt
.....\........\....\....\vopt0xv1q9
.....\........\....\....\vopt1rv48a
.....\........\....\....\vopt48h08a
.....\........\....\....\vopt899xc9
.....\........\....\....\voptcsytc9
.....\........\....\....\voptmryn17
.....\........\....\....\voptn7wbe9
.....\........\....\....\vopts8kj17
.....\........\....\....\voptsqh8e9
.....\........\....\....\vopttqga8a
.....\........\....\....\voptwr9f17
.....\........\....\....\voptx7678a
.....\........\....\....\voptx774e9
.....\........\....\....\_deps
.....\........\....\_temp
.....\........\....\_info
.....\........\....\_opt__lock
.....\........\modelsim.ini
.....\Quartus
.....\Source
.....\......\montre_num.vhd
.....\Testbench
.....\.........\montre_tb.vhd