FIFO Using MyFIFO_Block_Memory_v7_1with verilog code




File list:
prj_5
....\cores
....\.....\MyFIFO_Block_Memory_v7_1
....\.....\........................\doc
....\.....\........................\...\blk_mem_gen_ds512.pdf
....\.....\........................\...\blk_mem_gen_v7_1_vinfo.html
....\.....\........................\example_design
....\.....\........................\..............\MyFIFO_Block_Memory_v7_1_exdes.ucf
....\.....\........................\..............\MyFIFO_Block_Memory_v7_1_exdes.vhd
....\.....\........................\..............\MyFIFO_Block_Memory_v7_1_exdes.xdc
....\.....\........................\..............\MyFIFO_Block_Memory_v7_1_prod.vhd
....\.....\........................\implement
....\.....\........................\.........\implement.bat
....\.....\........................\.........\implement.sh
....\.....\........................\.........\planAhead_ise.bat
....\.....\........................\.........\planAhead_ise.sh
....\.....\........................\.........\planAhead_ise.tcl
....\.....\........................\.........\planAhead_rdn.bat
....\.....\........................\.........\planAhead_rdn.sh
....\.....\........................\.........\planAhead_rdn.tcl
....\.....\........................\.........\xst.prj
....\.....\........................\.........\xst.scr
....\.....\........................\simulation
....\.....\........................\..........\functional
....\.....\........................\..........\..........\simcmds.tcl
....\.....\........................\..........\..........\simulate_isim.bat
....\.....\........................\..........\..........\simulate_mti.bat
....\.....\........................\..........\..........\simulate_mti.do
....\.....\........................\..........\..........\simulate_mti.sh
....\.....\........................\..........\..........\simulate_ncsim.sh
....\.....\........................\..........\..........\simulate_vcs.sh
....\.....\........................\..........\..........\ucli_commands.key
....\.....\........................\..........\..........\vcs_session.tcl
....\.....\........................\..........\..........\wave_mti.do
....\.....\........................\..........\..........\wave_ncsim.sv
....\.....\........................\..........\timing
....\.....\........................\..........\......\simcmds.tcl
....\.....\........................\..........\......\simulate_isim.bat
....\.....\........................\..........\......\simulate_mti.bat
....\.....\........................\..........\......\simulate_mti.do
....\.....\........................\..........\......\simulate_mti.sh
....\.....\........................\..........\......\simulate_ncsim.sh
....\.....\........................\..........\......\simulate_vcs.sh
....\.....\........................\..........\......\ucli_commands.key
....\.....\........................\..........\......\vcs_session.tcl
....\.....\........................\..........\......\wave_mti.do
....\.....\........................\..........\......\wave_ncsim.sv
....\.....\........................\..........\addr_gen.vhd
....\.....\........................\..........\bmg_stim_gen.vhd
....\.....\........................\..........\bmg_tb_pkg.vhd
....\.....\........................\..........\checker.vhd
....\.....\........................\..........\data_gen.vhd
....\.....\........................\..........\MyFIFO_Block_Memory_v7_1_synth.vhd
....\.....\........................\..........\MyFIFO_Block_Memory_v7_1_tb.vhd
....\.....\........................\..........\random.vhd
....\.....\........................\blk_mem_gen_v7_1_readme.txt
....\.....\tmp
....\.....\...\_cg
....\.....\...\_xmsgs
....\.....\...\......\pn_parser.xmsgs
....\.....\...\......\xst.xmsgs
....\.....\...\MyFIFO_Block_Memory_v7_1.lso
....\.....\xlnx_auto_0_xdb
....\.....\coregen.cgc
....\.....\coregen.cgp
....\.....\MyFIFO_Block_Memory_v7_1.asy
....\.....\MyFIFO_Block_Memory_v7_1.gise
....\.....\MyFIFO_Block_Memory_v7_1.ngc
....\.....\MyFIFO_Block_Memory_v7_1.v
....\.....\MyFIFO_Block_Memory_v7_1.veo
....\.....\MyFIFO_Block_Memory_v7_1.xco
....\.....\MyFIFO_Block_Memory_v7_1.xise
....\.....\MyFIFO_Block_Memory_v7_1_flist.txt
....\.....\MyFIFO_Block_Memory_v7_1_xmdf.tcl
....\.....\summary.log
....\prj_5_lib
....\.........\hdl
....\.........\...\bbfifo_16x8.v
....\.........\...\ClockManager.v
....\.........\...\ClockManager.v.bak
....\.........\...\controller_fsm.v
....\.........\...\DataCapture.v
....\.........\...\DataCapture.v.bak
....\.........\...\datacapture_fsm.v
....\.........\...\datacapture_fsm.v.bak
....\.........\...\kcpsm3.v
....\.........\...\kcuart_rx.v
....\.........\...\kcuart_tx.v
....\.........\...\MyFIFO.v
....\.........\...\top_block_struct.v
....\.........\...\uart_clock.v
....\.........\...\uart_rx.v
....\.........\...\uart_tx.v
....\.........\hds
....\.........\...\.hdlsidedata
....\.........\...\............\_bbfifo_16x8.v._fpf
....\.........\...\............\_ClockManager.v._fpf
....\.........\...\............\_controller_fsm.v._fpf
....\.........\...\............\_DataCapture.v._fpf
....\.........\...\............\_datacapture_fsm.v._fpf
....\.........\...\............\_kcpsm3.v._fpf
....\.........\...\............\_kcuart_rx.v._fpf
....\.........\...\............\_kcuart_tx.v._fpf
....\.........\...\............\_MyFIFO.v._fpf
....\.........\...\............\_top_block_struct.v._fpf
....\.........\...\............\_uart_clock.v._fpf
....\.........\...\............\_uart_rx.v._fpf
....\.........\...\............\_uart_tx.v._fpf
....\.........\...\.xrf
....\.........\...\....\controller_fsm.xrf
....\.........\...\....\datacapture_fsm.xrf
....\.........\...\....\top_block_struct.xrf
....\.........\...\@clock@manager
....\.........\...\..............\interface
....\.........\...\..............\new_document.txt
....\.........\...\@controller
....\.........\...\...........\fsm.sm
....\.........\...\...........\fsm.sm.bak
....\.........\...\...........\interface
....\.........\...\@data@capture
....\.........\...\.............\fsm.sm
....\.........\...\.............\fsm.sm.bak
....\.........\...\.............\interface
....\.........\...\@mux
....\.........\...\....\interface
....\.........\...\....\new_document.txt
....\.........\...\....\new_document.txt.bak
....\.........\...\@my@f@i@f@o
....\.........\...\...........\struct.bd
....\.........\...\top_block
....\.........\...\.........\struct.bd
....\.........\...\.........\struct.bd.bak
....\.........\...\.........\symbol.sb
....\.........\...\.........\_struct.bd._fpf
....\.........\...\.........\_symbol.sb._fpf
....\.........\...\.cache.dat
....\.........\...\_@clock@manager._epf
....\.........\...\_@controller._epf
....\.........\...\_@data@capture._epf
....\.........\...\_@my@f@i@f@o._epf
....\.........\...\_top_block._epf
....\MyFIFO.v
....\prj_5.hdp
....\X_DCM.v