test the carry save adder program in verilog - source code download

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Classification:Hardware/embedded - VHDL Develop Development Tool:VHDL Sise:242 KB Upload time:2013/3/13 16:42:40 Uploader:ah2003 Download Statistics:

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the carry save adder program in verilog

File list:
test
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...\...\....\.........................\....\csa_test_isim_beh.exe_main.c
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...\...\....\.........................\....\m_00000000000074421303_1987096795.c
...\...\....\.........................\....\m_00000000000074421303_1987096795.didat
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...\...\....\.........................\GDBMI-In.txt
...\...\....\.........................\GDBMI-Out.txt
...\...\....\.........................\isimcrash.log
...\...\....\.........................\ISimEngine-DesignHierarchy.dbg
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...\...\csa_test_isim_beh.wdb
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...\...\csa_test_stx.prj
...\...\fuse.log
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...\csa.jpeg

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