b channel FIR filter verilog




File list:
8 channel FIR
............\syntmp
............\......\fir.msg
............\......\fir.plg
............\......\fir_flink.htm
............\......\fir_srr.htm
............\......\fir_toc.htm
............\......\top_design.msg
............\......\top_design.plg
............\......\top_design_flink.htm
............\......\top_design_srr.htm
............\......\top_design_toc.htm
............\verif
............\.....\fir.vif
............\.....\top_design.vif
............\_xmsgs
............\__projnav
............\.........\0000.gfl
............\.........\fir.ise_created
............\.........\top_design.ise_created
............\.........\__synProj.rsp
............\0000.dhp
............\0000.ise
............\0000.ise_ISE_Backup
............\0000.v
............\automake.log
............\case2s.v
............\case3s.v
............\fir.edn
............\fir.fse
............\fir.htm
............\fir.ncf
............\fir.prj
............\fir.sdc
............\fir.srd
............\fir.srm
............\fir.srr
............\fir.srs
............\fir.tlg
............\fir_compile.tcl
............\fir_map.tcl
............\rpt_fir.areasrr
............\rpt_fir_areasrr.htm
............\rpt_top_design.areasrr
............\rpt_top_design_areasrr.htm
............\state.txt
............\stdout.log
............\top_design.edn
............\top_design.fse
............\top_design.htm
............\top_design.ncf
............\top_design.prj
............\top_design.sdc
............\top_design.srd
............\top_design.srm
............\top_design.srr
............\top_design.srs
............\top_design.tlg
............\top_design.v
............\top_design_compile.tcl
............\top_design_map.tcl
............\__projnav.log