shift register in verilog
File list:
sage pir
.......\compile
.......\.......\add.bdeid
.......\.......\add.v
.......\.......\contents.lib~
.......\.......\sage pir.epr
.......\.......\sage pir.erf
.......\.......\sage pir.opt
.......\.......\sage pir.opv
.......\.......\sources.sth
.......\.......\test.bdeid
.......\.......\test.v
.......\.......\vcp_cmd.log
.......\.......\vsim.log
.......\.......\wave4.dat
.......\log
.......\...\add.htm
.......\...\console.log
.......\...\test.htm
.......\src
.......\...\4bit.v
.......\...\9-Detect.v
.......\...\9-detector.v
.......\...\add.bak
.......\...\contents.lib~
.......\...\dgoreg.v
.......\...\FD.v
.......\...\FourBit Counter.v
.......\...\frequency divider.v
.......\...\olddog.v
.......\...\seven converter.v
.......\...\test.bak
.......\...\test.bde
.......\0.mgf
.......\1.mgf
.......\2.mgf
.......\3.mgf
.......\bde.set
.......\compilation.order
.......\compile.cfg
.......\contents.lib~
.......\Edfmap.ini
.......\elaboration.log
.......\library.cfg
.......\projlib.cfg
.......\sage pir.adf
.......\sage pir.aws
.......\sage pir.wsp
.......\sage pir.wsw
.......\sage_pir.LIB
.......\sage_pir.rlb
.......\synthesis.order