some basic codes in verilod and thier test benches for understanding the basic verilog codes




File list:
codes
....\constraint_random_test_benches lab 9.doc
....\Day_6_Exercises.rtf
....\Direct TB.doc
....\FSM lab.doc
....\FSM Labs.doc
....\lab 1_Exercises.rtf
....\LAB 2- PORT CONNECTIONS.rtf
....\LAB 3- ALWAYS.rtf
....\LAB 4. FSM.rtf
....\lab 6 oop conceps lab .doc
....\lab 8 ASSERTIONS Lab.doc
....\lab 9 ASSERTIONS and OOP lab.doc
....\LAB EXERCISE 5- SYNTHESIS.rtf
....\lab exercise 6.doc
....\LAB-7.doc
....\lab1.docx
....\lab10 FSM Guidelines.doc
....\lab3.doc
....\LAB_4.doc
....\LAB_6.doc
....\LAB_8.doc
....\Lab_questions 7 and 8.doc
....\random_test_benches lab 7.doc