example of verilog code




File list:
vespa
....\vespa
....\.....\behavioral
....\.....\..........\behavioral.v
....\.....\..........\README
....\.....\example-asm
....\.....\...........\count.asm
....\.....\...........\ex1.asm
....\.....\...........\ex2.asm
....\.....\...........\ex3.asm
....\.....\...........\instr-test.asm
....\.....\...........\README
....\.....\pipeline
....\.....\........\alu.v
....\.....\........\comp.v
....\.....\........\dff.v
....\.....\........\hazard1.v
....\.....\........\inc4.v
....\.....\........\mem_mod.v
....\.....\........\mux2.v
....\.....\........\mux4.v
....\.....\........\opdec.v
....\.....\........\opdec_alu.v
....\.....\........\osc.v
....\.....\........\README
....\.....\........\reg_file.v
....\.....\........\setcc.v
....\.....\........\sext_mod.v
....\.....\........\stage1.v
....\.....\........\stage2.v
....\.....\........\stage3.v
....\.....\........\stage4.v
....\.....\........\stage5.v
....\.....\........\testcc.v
....\.....\........\vespa.v
....\.....\testbenches
....\.....\...........\alu
....\.....\...........\...\alu.v
....\.....\...........\...\checker.v
....\.....\...........\...\data_generator.v
....\.....\...........\...\opdec.v
....\.....\...........\...\osc.v
....\.....\...........\...\random_data_generator.v
....\.....\...........\...\testbench_alu.v
....\.....\...........\...\test_vectors
....\.....\...........\memory
....\.....\...........\......\checker.v
....\.....\...........\......\initialize.dat
....\.....\...........\......\mem_mod.v
....\.....\...........\......\osc.v
....\.....\...........\......\random_data_generator.v
....\.....\...........\......\testbench_mem.v
....\.....\...........\opdec
....\.....\...........\.....\checker.v
....\.....\...........\.....\data_generator.v
....\.....\...........\.....\opdec.v
....\.....\...........\.....\osc.v
....\.....\...........\.....\random_data_generator.v
....\.....\...........\.....\testbench_opdec.v
....\.....\...........\.....\test_vectors
....\.....\...........\setcc
....\.....\...........\.....\checker.v
....\.....\...........\.....\data_generator.v
....\.....\...........\.....\osc.v
....\.....\...........\.....\random_data_generator.v
....\.....\...........\.....\setcc.v
....\.....\...........\.....\testbench_setcc.v
....\.....\...........\.....\test_vectors
....\.....\...........\testcc
....\.....\...........\......\checker.v
....\.....\...........\......\data_generator.v
....\.....\...........\......\osc.v
....\.....\...........\......\random_data_generator.v
....\.....\...........\......\testbench_testcc.v
....\.....\...........\......\testcc.v
....\.....\...........\......\test_vectors
....\.....\...........\README
....\.....\vasm
....\.....\....\codegen.c
....\.....\....\gvars.h
....\.....\....\init.c
....\.....\....\Makefile
....\.....\....\misc.c
....\.....\....\README
....\.....\....\symtab.c
....\.....\....\vasm.c
....\.....\....\vasm.lex
....\.....\....\vasm.yacc
....\.....\README