an up down counter in verilog




File list:
bistabil.v
counter.jpg

counter4bCuCunterulNormal.JPG

counterPart1.v
counterPart2.v
counterPart3.v
counterPorti.v
counterPorti_tb.v
counterPorti_test.v
DW03_bictr_dcnto.pdf
mux21.v
pozna.JPG

pozna2.JPG

pozna3.JPG

pozna4.JPG

schema synplify.JPG

sumator1bit.v
sumator1bitNoCarryIn.v
sumator1bitNoCarryOut.v
test.v
transcript
UDCounter.v
UDCounter_tb.v
UDCounter_test.v