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multilyUnit1
  • Classification:Hardware/embedded - VHDL Develop
  • Development Tool:VHDL
  • Sise:150 KB
  • Upload time:2012/3/3 2:48:51
  • Uploader:pm429015
  • Download Statistics:
Description
a verilog programmed multiply unit algorithm full source code, has been tested.


synplify2.JPG

File list:
multiply.jpg
multiply.jpg
multiply.srm
multiply.srr
multiply.srs
multiply.tlg
multiply.v
multiply_tb.v
multiply_test.v
synplify.JPG
synplify.JPG
synplify2.JPG
synplify2.JPG
test.v
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