vhdl-simple-computer implementation of simple computer (alu, shared bus, register - source code download

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vhdl-simple-computer

Classification:Hardware/embedded - VHDL Develop Development Tool:VHDL Sise:967 KB Upload time:2009/12/5 12:26:55 Uploader:giperion Download Statistics:

Description

implementation of simple computer (alu, shared bus, register, input and output)in VHDL languageand an example of assembly code is present with complete description

File list:
vhdl simple computer
...................\chapters
...................\........\appendix a.doc
...................\........\appendix b.doc
...................\........\CHAPTER ONE new.doc
...................\........\CHAPTER THREE new.doc
...................\........\CHAPTER two new.doc
...................\........\content.doc
...................\........\New Text Document.txt
...................\........\Raied.txt
...................\........\reference.doc
...................\........\Thumbs.db
...................\........\untitled.bmp

...................\Raidproject2
...................\............\work
...................\............\....\acc
...................\............\....\...\pc4.asm
...................\............\....\...\pc4.dat
...................\............\....\...\_primary.dat
...................\............\....\alu
...................\............\....\...\pc3.asm
...................\............\....\...\pc3.dat
...................\............\....\...\_primary.dat
...................\............\....\cpu
...................\............\....\...\structure.asm
...................\............\....\...\structure.dat
...................\............\....\...\_primary.dat
...................\............\....\cpu_cfg
...................\............\....\.......\_primary.dat
...................\............\....\.......\_vhdl.asm
...................\............\....\ctrl
...................\............\....\....\fsm.asm
...................\............\....\....\fsm.dat
...................\............\....\....\_primary.dat
...................\............\....\dp
...................\............\....\..\struct.asm
...................\............\....\..\struct.dat
...................\............\....\..\_primary.dat
...................\............\....\mux
...................\............\....\...\pc1.asm
...................\............\....\...\pc1.dat
...................\............\....\...\_primary.dat
...................\............\....\mux_cfg
...................\............\....\.......\_primary.dat
...................\............\....\.......\_vhdl.asm
...................\............\....\myand
...................\............\....\.....\behavioral.asm
...................\............\....\.....\behavioral.dat
...................\............\....\.....\_primary.dat
...................\............\....\myand_cfg
...................\............\....\.........\_primary.dat
...................\............\....\.........\_vhdl.asm
...................\............\....\registerfile
...................\............\....\............\pc5.asm
...................\............\....\............\pc5.dat
...................\............\....\............\_primary.dat
...................\............\....\registerfile_cfg
...................\............\....\................\_primary.dat
...................\............\....\................\_vhdl.asm
...................\............\....\shifter
...................\............\....\.......\pc2.asm
...................\............\....\.......\pc2.dat
...................\............\....\.......\_primary.dat
...................\............\....\testbench
...................\............\....\.........\testbench_arch.asm
...................\............\....\.........\testbench_arch.dat
...................\............\....\.........\_primary.dat
...................\............\....\tristatebuffer
...................\............\....\..............\pc6.asm
...................\............\....\..............\pc6.dat
...................\............\....\..............\_primary.dat
...................\............\....\_info
...................\............\xst
...................\............\...\synopsys
...................\............\...\........\hdpdeps.ref
...................\............\...\work
...................\............\...\....\sub00
...................\............\...\....\.....\vhpl00.vho
...................\............\...\....\.....\vhpl01.vho
...................\............\...\....\.....\vhpl02.vho
...................\............\...\....\.....\vhpl03.vho
...................\............\...\....\.....\vhpl04.vho
...................\............\...\....\.....\vhpl05.vho
...................\............\...\....\.....\vhpl06.vho
...................\............\...\....\.....\vhpl07.vho
...................\............\...\....\.....\vhpl08.vho
...................\............\...\....\.....\vhpl09.vho
...................\............\...\....\.....\vhpl10.vho
...................\............\...\....\.....\vhpl11.vho
...................\............\...\....\.....\vhpl12.vho
...................\............\...\....\.....\vhpl13.vho
...................\............\...\....\.....\vhpl14.vho
...................\............\...\....\.....\vhpl15.vho
...................\............\...\....\.....\vhpl16.vho
...................\............\...\....\.....\vhpl17.vho
...................\............\...\....\.....\vhpl18.vho
...................\............\...\....\.....\vhpl19.vho
...................\............\...\....\.....\vhpl20.vho
...................\............\...\....\.....\vhpl21.vho
...................\............\...\....\.....\vhpl22.vho
...................\............\...\....\.....\vhpl23.vho
...................\............\...\....\hdpdeps.ref
...................\............\...\....\vhdllib.ref
...................\............\acc.cup
...................\............\acc.jhd
...................\............\acc.ngc
...................\............\acc.prj
...................\............\acc.syr
...................\............\acc.vhd
...................\............\acc.xst
...................\............\acc._prj
...................\............\alu.cup
...................\............\ALU.jhd
...................\............\alu.ngc
...................\............\alu.prj
...................\............\alu.syr
...................\............\ALU.vhd
...................\............\alu.xst
...................\............\alu._prj
...................\............\automake.err
...................\............\automake.log
...................\............\cpu.cup
...................\............\cpu.jhd
...................\............\cpu.ngc
...................\............\cpu.prj
...................\............\cpu.syr
...................\............\cpu.vhd
...................\............\cpu.xst
...................\............\cpu._prj
...................\............\ctrl.cup
...................\............\ctrl.jhd
...................\............\ctrl.ngc
...................\............\ctrl.prj
...................\............\ctrl.syr
...................\............\ctrl.vhd
...................\............\ctrl.xst
...................\............\ctrl._prj
...................\............\datapath.cup
...................\............\datapath.jhd
...................\............\datapath.ngc
...................\............\datapath.prj
...................\............\datapath.syr
...................\............\datapath.vhd
...................\............\datapath.xst
...................\............\datapath._prj
...................\............\larger.cup
...................\............\larger.jhd
...................\............\larger.ngc
...................\............\larger.prj
...................\............\larger.syr
...................\............\larger.vhd
...................\............\larger.xst
...................\............\larger._prj
...................\............\mux.cup
...................\............\mux.jhd
...................\............\mux.ngc
...................\............\mux.prj
...................\............\mux.syr
...................\............\mux.vhd
...................\............\mux.xst
...................\............\mux._prj
...................\............\myand.cup
...................\............\myand.jhd
...................\............\myand.ngc
...................\............\myand.prj
...................\............\myand.syr
...................\............\myand.vhd
...................\............\myand.xst
...................\............\myand._prj
...................\............\program
...................\............\raidproject.jid
...................\............\Raidproject.npl
...................\............\Raidproject.ptf
...................\............\registerfile.cup
...................\............\REGISTERFILE.jhd
...................\............\registerfile.ngc
...................\............\registerfile.prj
...................\............\registerfile.syr
...................\............\REGISTERFILE.vhd
...................\............\registerfile.xst
...................\............\registerfile._prj
...................\............\results.txt
...................\............\shifter.cup
...................\............\SHIFTER.jhd
...................\............\shifter.ngc
...................\............\shifter.prj
...................\............\shifter.syr
...................\............\SHIFTER.vhd
...................\............\shifter.xst
...................\............\shifter._prj
...................\............\testmux.ado
...................\............\testmux.ant
...................\............\testmux.fdo
...................\............\testmux.jhd
...................\............\testmux.tbw
...................\............\testmux.udo
...................\............\testmux.vhw
...................\............\testmycct.ant
...................\............\testmycct.fdo
...................\............\testmycct.jhd
...................\............\testmycct.tbw
...................\............\testmycct.udo
...................\............\testmycct.vhw
...................\............\test_cpu.ant
...................\............\test_cpu.fdo
...................\............\test_cpu.jhd
...................\............\test_cpu.tbw
...................\............\test_cpu.udo
...................\............\test_cpu.vhw
...................\............\test_rf.ant
...................\............\test_rf.fdo
...................\............\test_rf.jhd
...................\............\test_rf.tbw
...................\............\test_rf.udo
...................\............\test_rf.vhw
...................\............\transcript
...................\............\tristatebuffer.jhd
...................\............\tristatebuffer.vhd
...................\............\vsim.wlf
...................\............\_hb_cmds
...................\............\_msim_simBehavVhdlModel.rsp
...................\............\_msim_simBehavVhdlModel_exewrap.rsp
...................\............\_vhdTOfdo_exewrap.rsp
...................\............\__acc_2prj_exewrap.rsp
...................\............\__alu_2prj_exewrap.rsp
...................\............\__antTOano.rsp
...................\............\__checkModelSim.pl
...................\............\__cpu_2prj_exewrap.rsp
...................\............\__ctrl_2prj_exewrap.rsp
...................\............\__datapath_2prj_exewrap.rsp
...................\............\__larger_2prj_exewrap.rsp
...................\............\__msimOption.rsp
...................\............\__mux_2prj_exewrap.rsp
...................\............\__myand_2prj_exewrap.rsp
...................\............\__projnav.log
...................\............\__registerfile_2prj_exewrap.rsp
...................\............\__runBencher.tcl
...................\............\__runBencherAnno.tcl
...................\............\__shifter_2prj_exewrap.rsp
...................\............\__updateTBW_exewrap.rsp
...................\............\__vhdTOfdo.rsp

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