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  • Classification:Hardware/embedded - VHDL Develop
  • Development Tool:DOS
  • Sise:237 KB
  • Upload time:2011/5/24 21:27:50
  • Uploader:john3381
  • Download Statistics:
Description
verilog code for simple project


NoD-NoDInSensitivityList.JPG

File list:
CAD HW
.....\D - No Sensitivity List.JPG
D-NoSensitivityList.JPG
.....\HW Final.docx
.....\No D - No D In Sensitivity List.JPG
NoD-NoDInSensitivityList.JPG
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