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Counter_Design_Block
  • Classification:Hardware/embedded - VHDL Develop
  • Development Tool:VHDL
  • Sise:11.0 KB
  • Upload time:2011/5/25 7:40:09
  • Uploader:abay03
  • Download Statistics:
Description
Here is a code for a simple counter based on verilog


vcount_sim.gif

File list:
first_counter.v
first_counter_tb.v
vcount.gif
vcount.gif
vcount_sim.gif
vcount_sim.gif
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