mips files uploaded full verilog sourse code




File list:
mips_file
........\work
........\....\@a@l@u_@control
........\....\...............\verilog.prw
........\....\...............\verilog.psm
........\....\...............\_primary.dat
........\....\...............\_primary.dbs
........\....\...............\_primary.vhd
........\....\@alu_32
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\@left@shifter_2bit
........\....\..................\verilog.prw
........\....\..................\verilog.psm
........\....\..................\_primary.dat
........\....\..................\_primary.dbs
........\....\..................\_primary.vhd
........\....\@registers
........\....\..........\verilog.prw
........\....\..........\verilog.psm
........\....\..........\_primary.dat
........\....\..........\_primary.dbs
........\....\..........\_primary.vhd
........\....\adder_brach
........\....\...........\verilog.prw
........\....\...........\verilog.psm
........\....\...........\_primary.dat
........\....\...........\_primary.dbs
........\....\...........\_primary.vhd
........\....\alu_full
........\....\........\verilog.prw
........\....\........\verilog.psm
........\....\........\_primary.dat
........\....\........\_primary.dbs
........\....\........\_primary.vhd
........\....\andgate
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\brach_adder_cum_shifter
........\....\.......................\verilog.prw
........\....\.......................\verilog.psm
........\....\.......................\_primary.dat
........\....\.......................\_primary.dbs
........\....\.......................\_primary.vhd
........\....\datamememroy
........\....\............\verilog.prw
........\....\............\verilog.psm
........\....\............\_primary.dat
........\....\............\_primary.dbs
........\....\............\_primary.vhd
........\....\instruction_memory
........\....\..................\verilog.prw
........\....\..................\verilog.psm
........\....\..................\_primary.dat
........\....\..................\_primary.dbs
........\....\..................\_primary.vhd
........\....\instuction_divider
........\....\..................\verilog.prw
........\....\..................\verilog.psm
........\....\..................\_primary.dat
........\....\..................\_primary.dbs
........\....\..................\_primary.vhd
........\....\j_addr
........\....\......\verilog.prw
........\....\......\verilog.psm
........\....\......\_primary.dat
........\....\......\_primary.dbs
........\....\......\_primary.vhd
........\....\left_shifter_28
........\....\...............\verilog.prw
........\....\...............\verilog.psm
........\....\...............\_primary.dat
........\....\...............\_primary.dbs
........\....\...............\_primary.vhd
........\....\mipsprocessor
........\....\.............\verilog.prw
........\....\.............\verilog.psm
........\....\.............\_primary.dat
........\....\.............\_primary.dbs
........\....\.............\_primary.vhd
........\....\mips_cntr
........\....\.........\verilog.prw
........\....\.........\verilog.psm
........\....\.........\_primary.dat
........\....\.........\_primary.dbs
........\....\.........\_primary.vhd
........\....\mux5_2x1
........\....\........\verilog.prw
........\....\........\verilog.psm
........\....\........\_primary.dat
........\....\........\_primary.dbs
........\....\........\_primary.vhd
........\....\mux_32
........\....\......\verilog.prw
........\....\......\verilog.psm
........\....\......\_primary.dat
........\....\......\_primary.dbs
........\....\......\_primary.vhd
........\....\pc_adder
........\....\........\verilog.prw
........\....\........\verilog.psm
........\....\........\_primary.dat
........\....\........\_primary.dbs
........\....\........\_primary.vhd
........\....\pc_changer
........\....\..........\verilog.prw
........\....\..........\verilog.psm
........\....\..........\_primary.dat
........\....\..........\_primary.dbs
........\....\..........\_primary.vhd
........\....\program_counter
........\....\...............\verilog.prw
........\....\...............\verilog.psm
........\....\...............\_primary.dat
........\....\...............\_primary.dbs
........\....\...............\_primary.vhd
........\....\second_testing
........\....\..............\verilog.prw
........\....\..............\verilog.psm
........\....\..............\_primary.dat
........\....\..............\_primary.dbs
........\....\..............\_primary.vhd
........\....\sign_extensionunit
........\....\..................\verilog.prw
........\....\..................\verilog.psm
........\....\..................\_primary.dat
........\....\..................\_primary.dbs
........\....\..................\_primary.vhd
........\....\_temp
........\....\_info
........\....\_vmake
........\adder_branch.v
........\adder_branch.v.bak
........\Alu_32.v
........\Alu_32.v.bak
........\ALU_Control.v
........\ALU_Control.v.bak
........\alu_full.v
........\alu_full.v.bak
........\andgate.v
........\andgate.v.bak
........\brach_adder_cum_shifter.v
........\brach_adder_cum_shifter.v.bak
........\datamememroy.v
........\datamememroy.v.bak
........\instruction_memory.v
........\instruction_memory.v.bak
........\instuction_divider.v
........\instuction_divider.v.bak
........\j_addr.v
........\j_addr.v.bak
........\left_shifter.v
........\left_shifter.v.bak
........\left_shifter_28.v
........\left_shifter_28.v.bak
........\mips.v
........\mips.v.bak
........\mips_cntr.v
........\mips_cntr.v.bak
........\mips_processor.cr.mti
........\mips_processor.mpf
........\mux5_2x1.v
........\mux5_2x1.v.bak
........\mux_32.v
........\mux_32.v.bak
........\pc_adder.v
........\pc_adder.v.bak
........\pc_changer.v
........\pc_changer.v.bak
........\program_conter.v
........\program_conter.v.bak
........\registers.v
........\registers.v.bak
........\sign_extensionunit.v
........\sign_extensionunit.v.bak
........\testing.v
........\testing.v.bak
........\vsim.wlf