DE0 VGA controlclk_div, ctrl, pattern




File list:
db
.\.cmp.kpt
.\DIV3_VGA.(0).cnf.cdb
.\DIV3_VGA.(0).cnf.hdb
.\DIV3_VGA.(1).cnf.cdb
.\DIV3_VGA.(1).cnf.hdb
.\DIV3_VGA.(2).cnf.cdb
.\DIV3_VGA.(2).cnf.hdb
.\DIV3_VGA.(3).cnf.cdb
.\DIV3_VGA.(3).cnf.hdb
.\DIV3_VGA.(4).cnf.cdb
.\DIV3_VGA.(4).cnf.hdb
.\DIV3_VGA.(5).cnf.cdb
.\DIV3_VGA.(5).cnf.hdb
.\DIV3_VGA.(6).cnf.cdb
.\DIV3_VGA.(6).cnf.hdb
.\DIV3_VGA.ace_cmp.bpm
.\DIV3_VGA.ace_cmp.cdb
.\DIV3_VGA.ace_cmp.hdb
.\DIV3_VGA.asm.qmsg
.\DIV3_VGA.asm.rdb
.\DIV3_VGA.asm_labs.ddb
.\DIV3_VGA.cbx.xml
.\DIV3_VGA.cmp.bpm
.\DIV3_VGA.cmp.cdb
.\DIV3_VGA.cmp.hdb
.\DIV3_VGA.cmp.idb
.\DIV3_VGA.cmp.logdb
.\DIV3_VGA.cmp.rdb
.\DIV3_VGA.cmp_merge.kpt
.\DIV3_VGA.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.\DIV3_VGA.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
.\DIV3_VGA.db_info
.\DIV3_VGA.eco.cdb
.\DIV3_VGA.fit.qmsg
.\DIV3_VGA.hier_info
.\DIV3_VGA.hif
.\DIV3_VGA.ipinfo
.\DIV3_VGA.lpc.html
.\DIV3_VGA.lpc.rdb
.\DIV3_VGA.lpc.txt
.\DIV3_VGA.map.ammdb
.\DIV3_VGA.map.bpm
.\DIV3_VGA.map.cdb
.\DIV3_VGA.map.hdb
.\DIV3_VGA.map.kpt
.\DIV3_VGA.map.logdb
.\DIV3_VGA.map.qmsg
.\DIV3_VGA.map.rdb
.\DIV3_VGA.map_bb.cdb
.\DIV3_VGA.map_bb.hdb
.\DIV3_VGA.map_bb.logdb
.\DIV3_VGA.pplq.rdb
.\DIV3_VGA.pre_map.hdb
.\DIV3_VGA.pti_db_list.ddb
.\DIV3_VGA.qns
.\DIV3_VGA.root_partition.map.reg_db.cdb
.\DIV3_VGA.routing.rdb
.\DIV3_VGA.rtlv.hdb
.\DIV3_VGA.rtlv_sg.cdb
.\DIV3_VGA.rtlv_sg_swap.cdb
.\DIV3_VGA.sgdiff.cdb
.\DIV3_VGA.sgdiff.hdb
.\DIV3_VGA.sld_design_entry.sci
.\DIV3_VGA.sld_design_entry_dsc.sci
.\DIV3_VGA.smart_action.txt
.\DIV3_VGA.sta.qmsg
.\DIV3_VGA.sta.rdb
.\DIV3_VGA.sta_cmp.6_slow_1200mv_85c.tdb
.\DIV3_VGA.taw.rdb
.\DIV3_VGA.tiscmp.fast_1200mv_0c.ddb
.\DIV3_VGA.tiscmp.slow_1200mv_0c.ddb
.\DIV3_VGA.tiscmp.slow_1200mv_85c.ddb
.\DIV3_VGA.tis_db_list.ddb
.\DIV3_VGA.tmw_info
.\DIV3_VGA.vpr.ammdb
.\logic_util_heursitic.dat
.\prev_cmp_DIV3_VGA.qmsg
.\VGA_CLK_altpll.v
greybox_tmp
..........\cbx_args.txt
incremental_db
.............\compiled_partitions
.............\...................\DIV3_VGA.db_info
.............\...................\DIV3_VGA.root_partition.cmp.ammdb
.............\...................\DIV3_VGA.root_partition.cmp.cdb
.............\...................\DIV3_VGA.root_partition.cmp.dfp
.............\...................\DIV3_VGA.root_partition.cmp.hdb
.............\...................\DIV3_VGA.root_partition.cmp.logdb
.............\...................\DIV3_VGA.root_partition.cmp.rcfdb
.............\...................\DIV3_VGA.root_partition.map.cdb
.............\...................\DIV3_VGA.root_partition.map.dpi
.............\...................\DIV3_VGA.root_partition.map.hbdb.cdb
.............\...................\DIV3_VGA.root_partition.map.hbdb.hb_info
.............\...................\DIV3_VGA.root_partition.map.hbdb.hdb
.............\...................\DIV3_VGA.root_partition.map.hbdb.sig
.............\...................\DIV3_VGA.root_partition.map.hdb
.............\...................\DIV3_VGA.root_partition.map.kpt
.............\README
output_files
...........\greybox_tmp
...........\...........\cbx_args.txt
...........\DIV3_VGA.asm.rpt
...........\DIV3_VGA.cdf
...........\DIV3_VGA.done
...........\DIV3_VGA.fit.rpt
...........\DIV3_VGA.fit.smsg
...........\DIV3_VGA.fit.summary
...........\DIV3_VGA.flow.rpt
...........\DIV3_VGA.jdi
...........\DIV3_VGA.map.rpt
...........\DIV3_VGA.map.summary
...........\DIV3_VGA.pin
...........\DIV3_VGA.pti_db_list.ddb
...........\DIV3_VGA.sof
...........\DIV3_VGA.sta.rpt
...........\DIV3_VGA.sta.summary
...........\DIV3_VGA.tis_db_list.ddb
...........\VGA_CLK.ppf
...........\VGA_CLK.qip
...........\VGA_CLK.v
...........\VGA_CLK_bb.v
DIV3_VGA.out.sdc
DIV3_VGA.qpf
DIV3_VGA.qsf
DIV3_VGA.qws
DIV3_VGA.sdc
DIV3_VGA.v
DIV3_VGA.v.bak
PLLJ_PLLSPE_INFO.txt
VGA_CLK.qip
VGA_CLK.v
VGA_Ctrl.v
VGA_Ctrl.v.bak
VGA_Pattern.v
VGA_Pattern.v.bak