vhdl verilog for LVDS altera stratix4 - source code download

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Classification:Hardware/embedded - VHDL Develop Development Tool:VHDL Sise:52.0 KB Upload time:2014/2/14 4:26:27 Uploader:zani Download Statistics:

Description

verilog for LVDS altera stratix4

File list:
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.............\altlvds.qpf
.............\altlvds.qsf
.............\altlvds.qws
.............\altlvds.v
.............\altlvds.v.bak
.............\altlvds_nativelink_simulation.rpt
.............\Block2.bdf
.............\Block2.v
.............\Block2.v.bak
.............\Block2_tb.v
.............\Block2_tb.v.bak
.............\loop_tb.v
.............\loop_tb.v.bak
.............\pll.bsf
.............\pll.cmp
.............\pll.inc
.............\pll.ppf
.............\pll.qip
.............\pll.v
.............\PLLJ_PLLSPE_INFO.txt
.............\pll_bb.v
.............\pll_inst.v
.............\pll_syn.v
.............\rx_lvds.bsf
.............\rx_lvds.cmp
.............\rx_lvds.inc
.............\rx_lvds.ppf
.............\rx_lvds.qip
.............\rx_lvds.v
.............\rx_lvds_bb.v
.............\rx_lvds_inst.v
.............\rx_lvds_syn.v
.............\tx_lvds.bsf
.............\tx_lvds.cmp
.............\tx_lvds.inc
.............\tx_lvds.ppf
.............\tx_lvds.qip
.............\tx_lvds.v
.............\tx_lvds_bb.v
.............\tx_lvds_inst.v
.............\tx_lvds_syn.v

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