VHDL CODE FOR CORDIC ALGORITHM FOR COS AND SINE GENERATION




File list:
Cordic
.....\Cordic
.....\......\C-sources
.....\......\.........\genvect.bat
.....\......\.........\gen_testvector.c
.....\......\.........\gen_testvector.exe
.....\......\hdl
.....\......\...\addsub_synthesis.vhd
.....\......\...\atan32_Arch1.vhd
.....\......\...\clockgen_rtl.vhd
.....\......\...\cordic_pkg_pkg.vhd
.....\......\...\cordic_synthesis.vhd
.....\......\...\cordic_tb_struct.vhd
.....\......\...\cordic_tester_behavioral.vhd
.....\......\...\fsm_synthesis.vhd
.....\......\...\shiftn_synthesis.vhd
.....\......\src
.....\......\...\.xrf
.....\......\...\....\addsub_synthesis.xrf
.....\......\...\....\atan32_Arch1.xrf
.....\......\...\....\clockgen_rtl.xrf
.....\......\...\....\cordic_pkg_pkg.xrf
.....\......\...\....\cordic_pkg_pkg_body.xrf
.....\......\...\....\cordic_synthesis.xrf
.....\......\...\....\cordic_tb_struct.xrf
.....\......\...\....\cordic_tester_behavioral.xrf
.....\......\...\....\fsm_synthesis.xrf
.....\......\...\....\shiftn_synthesis.xrf
.....\......\...\addsub
.....\......\...\......\synthesis.vhd.info
.....\......\...\......\..................\structure.dh
.....\......\...\......\default_view
.....\......\...\......\symbol.sb
.....\......\...\......\synthesis.vhd
.....\......\...\atan32
.....\......\...\......\Arch1.vhd.info
.....\......\...\......\..............\structure.dh
.....\......\...\......\Arch1.vhd
.....\......\...\......\default_view
.....\......\...\......\symbol.sb
.....\......\...\clockgen
.....\......\...\........\rtl.vhd.info
.....\......\...\........\............\structure.dh
.....\......\...\........\default_view
.....\......\...\........\rtl.vhd
.....\......\...\........\symbol.sb
.....\......\...\cordic
.....\......\...\......\default_view
.....\......\...\......\symbol.sb
.....\......\...\......\synthesis.bd
.....\......\...\cordic_pkg
.....\......\...\..........\cordic_pkg.info
.....\......\...\..........\...............\structure.dh
.....\......\...\..........\_package.vhd
.....\......\...\..........\_package_body.vhd
.....\......\...\cordic_tb
.....\......\...\.........\default_view
.....\......\...\.........\struct.bd
.....\......\...\.........\symbol.sb
.....\......\...\cordic_tester
.....\......\...\.............\behavioral.vhd.info
.....\......\...\.............\...................\structure.dh
.....\......\...\.............\...................\testvec.txt
.....\......\...\.............\behavioral.vhd
.....\......\...\.............\default_view
.....\......\...\.............\interface
.....\......\...\fsm
.....\......\...\...\default_view
.....\......\...\...\symbol.sb
.....\......\...\...\synthesis.sm
.....\......\...\shiftn
.....\......\...\......\synthesis.vhd.info
.....\......\...\......\..................\structure.dh
.....\......\...\......\default_view
.....\......\...\......\symbol.sb
.....\......\...\......\synthesis.vhd
.....\......\work_mti
.....\......\........\compile.scr
.....\......\........\modelsim.ini
.....\......\........\modelsim.tcl
.....\......\........\tb.do
.....\......\........\tb.scr
.....\......\........\_info
.....\......\work_ps
.....\......\.......\add_files.tcl
.....\.DS_Store
__MACOSX
.......\Cordic
.......\......\Cordic
.......\......\......\C-sources
.......\......\......\.........\._genvect.bat
.......\......\......\.........\._gen_testvector.c
.......\......\......\.........\._gen_testvector.exe
.......\......\......\hdl
.......\......\......\...\._addsub_synthesis.vhd
.......\......\......\...\._atan32_Arch1.vhd
.......\......\......\...\._clockgen_rtl.vhd
.......\......\......\...\._cordic_pkg_pkg.vhd
.......\......\......\...\._cordic_synthesis.vhd
.......\......\......\...\._cordic_tb_struct.vhd
.......\......\......\...\._cordic_tester_behavioral.vhd
.......\......\......\...\._fsm_synthesis.vhd
.......\......\......\...\._shiftn_synthesis.vhd
.......\......\......\src
.......\......\......\...\.xrf
.......\......\......\...\....\._addsub_synthesis.xrf
.......\......\......\...\....\._atan32_Arch1.xrf
.......\......\......\...\....\._clockgen_rtl.xrf
.......\......\......\...\....\._cordic_pkg_pkg.xrf
.......\......\......\...\....\._cordic_pkg_pkg_body.xrf
.......\......\......\...\....\._cordic_synthesis.xrf
.......\......\......\...\....\._cordic_tb_struct.xrf
.......\......\......\...\....\._cordic_tester_behavioral.xrf
.......\......\......\...\....\._fsm_synthesis.xrf
.......\......\......\...\....\._shiftn_synthesis.xrf
.......\......\......\...\addsub
.......\......\......\...\......\synthesis.vhd.info
.......\......\......\...\......\..................\._structure.dh
.......\......\......\...\......\._default_view
.......\......\......\...\......\._symbol.sb
.......\......\......\...\......\._synthesis.vhd
.......\......\......\...\......\._synthesis.vhd.info
.......\......\......\...\atan32
.......\......\......\...\......\Arch1.vhd.info
.......\......\......\...\......\..............\._structure.dh
.......\......\......\...\......\._Arch1.vhd
.......\......\......\...\......\._Arch1.vhd.info
.......\......\......\...\......\._default_view
.......\......\......\...\......\._symbol.sb
.......\......\......\...\clockgen
.......\......\......\...\........\rtl.vhd.info
.......\......\......\...\........\............\._structure.dh
.......\......\......\...\........\._default_view
.......\......\......\...\........\._rtl.vhd
.......\......\......\...\........\._rtl.vhd.info
.......\......\......\...\........\._symbol.sb
.......\......\......\...\cordic
.......\......\......\...\......\._default_view
.......\......\......\...\......\._symbol.sb
.......\......\......\...\......\._synthesis.bd
.......\......\......\...\cordic_pkg
.......\......\......\...\..........\cordic_pkg.info
.......\......\......\...\..........\...............\._structure.dh
.......\......\......\...\..........\._cordic_pkg.info
.......\......\......\...\..........\.__package.vhd
.......\......\......\...\..........\.__package_body.vhd
.......\......\......\...\cordic_tb
.......\......\......\...\.........\._default_view
.......\......\......\...\.........\._struct.bd
.......\......\......\...\.........\._symbol.sb
.......\......\......\...\cordic_tester
.......\......\......\...\.............\behavioral.vhd.info
.......\......\......\...\.............\...................\._structure.dh
.......\......\......\...\.............\...................\._testvec.txt
.......\......\......\...\.............\._behavioral.vhd
.......\......\......\...\.............\._behavioral.vhd.info
.......\......\......\...\.............\._default_view
.......\......\......\...\.............\._interface
.......\......\......\...\fsm
.......\......\......\...\...\._default_view
.......\......\......\...\...\._symbol.sb
.......\......\......\...\...\._synthesis.sm
.......\......\......\...\shiftn
.......\......\......\...\......\synthesis.vhd.info
.......\......\......\...\......\..................\._structure.dh
.......\......\......\...\......\._default_view
.......\......\......\...\......\._symbol.sb
.......\......\......\...\......\._synthesis.vhd
.......\......\......\...\......\._synthesis.vhd.info
.......\......\......\...\._.xrf
.......\......\......\...\._addsub
.......\......\......\...\._atan32
.......\......\......\...\._clockgen
.......\......\......\...\._cordic
.......\......\......\...\._cordic_pkg
.......\......\......\...\._cordic_tb
.......\......\......\...\._cordic_tester
.......\......\......\...\._fsm
.......\......\......\...\._shiftn
.......\......\......\work_mti
.......\......\......\........\._compile.scr
.......\......\......\........\._modelsim.ini
.......\......\......\........\._modelsim.tcl
.......\......\......\........\._tb.do
.......\......\......\........\._tb.scr
.......\......\......\........\.__info
.......\......\......\work_ps
.......\......\......\.......\._add_files.tcl
.......\......\......\._C-sources
.......\......\......\._hdl
.......\......\......\._src
.......\......\......\._work_mti
.......\......\......\._work_ps
.......\......\._.DS_Store
.......\......\._Cordic