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mips
  • Classification:Hardware/embedded - VHDL Develop
  • Development Tool:VHDL
  • Sise:2.62 MB
  • Upload time:2011/5/24 20:37:34
  • Uploader:tcxhb123
  • Download Statistics:
Description
in verilog 8bit mips processor


xpla3_logo.jpg

File list:
MUX_2to1_html
............\fit
............\...\applet.htm
............\...\applet.js
............\...\appletref.htm
............\...\ascii.htm
............\...\ascii.tmp
............\...\asciidoc.htm
............\...\backtop.jpg
backtop.jpg
............\...\beginstraight.gif
beginstraight.gif
............\...\blank.gif
blank.gif
............\...\blank.htm
............\...\briefview.jpg
briefview.jpg
............\...\check.htm
............\...\checkNS4.htm
............\...\contact.gif
contact.gif
............\...\coolrunnerII_logo.jpg
coolrunnerII_logo.jpg
............\...\coolrunner_logo.jpg
coolrunner_logo.jpg
............\...\defeqns.htm
............\...\education.gif
education.gif
............\...\endmkt.gif
endmkt.gif
............\...\eqns.htm
............\...\eqns.js
............\...\equations.gif
equations.gif
............\...\equations.htm
............\...\equationsdoc.htm
............\...\errors.js
............\...\errors1.gif
errors1.gif
............\...\errors2.gif
errors2.gif
............\...\errorsdoc.htm
............\...\errs.htm
............\...\failtable.htm
............\...\failtable.js
............\...\failtabledoc.htm
............\...\fb.gif
fb.gif
............\...\fb1.gif
fb1.gif
............\...\fbs.htm
............\...\fbs.js
............\...\fbsdoc.htm
............\...\fbs_FB1.htm
............\...\fbs_FB2.htm
............\...\fbs_FB3.htm
............\...\fbs_FB4.htm
............\...\fbs_FB5.htm
............\...\fbs_FB6.htm
............\...\fbs_FB7.htm
............\...\fbs_FB8.htm
............\...\fbs_FBdoc.htm
............\...\fbview.jpg
fbview.jpg
............\...\functionblock.gif
functionblock.gif
............\...\genmsg.htm
............\...\header.gif
header.gif
............\...\home.gif
home.gif
............\...\index.htm
............\...\inputleft.htm
............\...\inputleft.js
............\...\inputleftdoc.htm
............\...\leftnav.htm
............\...\leftnav.js
............\...\legend.gif
legend.gif
............\...\legend.jpg
legend.jpg
............\...\logicleft.htm
............\...\logicleft.js
............\...\logicleftdoc.htm
............\...\logiclegend.htm
............\...\logiclegendV.htm
............\...\logic_legXbr.htm
............\...\logic_legXC95.htm
............\...\logic_legXpla3.htm
............\...\macrocell.gif
macrocell.gif
............\...\mapinputdoc.htm
............\...\mapinput_00.htm
............\...\mapinput_01.htm
............\...\mapinput_02.htm
............\...\maplogic.js
............\...\maplogicdoc.htm
............\...\maplogic_00.htm
............\...\maplogic_01.htm
............\...\maplogic_02.htm
............\...\newappletref.htm
............\...\next.jpg
next.jpg
............\...\ns4plugin.js
............\...\options.htm
............\...\optionsdoc.htm
............\...\paths.js
............\...\pin.gif
pin.gif
............\...\pindiagram.gif
pindiagram.gif
............\...\pinlegend.htm
............\...\pinlegendV.htm
............\...\pins.htm
............\...\pins.js
............\...\pinsdoc.htm
............\...\pinview.jpg
pinview.jpg
............\...\pin_legXbr.htm
............\...\pin_legXC95.htm
............\...\pin_legXpla3.htm
............\...\plugin.js
............\...\prev.jpg
prev.jpg
............\...\print.jpg
print.jpg
............\...\products.gif
products.gif
............\...\purchase.gif
purchase.gif
............\...\report.htm
............\...\result.htm
............\...\search.gif
search.gif
............\...\spacer.gif
spacer.gif
............\...\style.css
............\...\summary.htm
............\...\summary.js
............\...\summarydoc.htm
............\...\support.gif
support.gif
............\...\time.htm
............\...\tooltips.js
............\...\topnav.htm
............\...\topnav.js
............\...\unmapinputdoc.htm
............\...\unmaplogicdoc.htm
............\...\verboseview.jpg
verboseview.jpg
............\...\view.gif
view.gif
............\...\wait.htm
............\...\xc9500xl_logo.gif
xc9500xl_logo.gif
............\...\xc9500xl_logo.jpg
xc9500xl_logo.jpg
............\...\xc9500xv_logo.jpg
xc9500xv_logo.jpg
............\...\xc9500_logo.gif
xc9500_logo.gif
............\...\xc9500_logo.jpg
xc9500_logo.jpg
............\...\xcenter.gif
xcenter.gif
............\...\xlogo.gif
xlogo.gif
............\...\xml5.jpg
xml5.jpg
............\...\xml6.jpg
xml6.jpg
............\...\xml7.jpg
xml7.jpg
............\...\xml8.jpg
xml8.jpg
............\images
............\......\acr2_logo.jpg
acr2_logo.jpg
............\......\blackBar.jpg
blackBar.jpg
............\......\cpldBanner.jpg
cpldBanner.jpg
............\......\cr2s_logo.jpg
cr2s_logo.jpg
............\......\fitterRpt.jpg
fitterRpt.jpg
............\......\logo.jpg
logo.jpg
............\......\spacer.jpg
spacer.jpg
............\......\timingRpt.jpg
timingRpt.jpg
............\......\xa9500xl_logo.jpg
xa9500xl_logo.jpg
............\......\xbr_logo.jpg
xbr_logo.jpg
............\......\xc9500xl_logo.jpg
xc9500xl_logo.jpg
............\......\xc9500xv_logo.jpg
xc9500xv_logo.jpg
............\......\xc9500_logo.jpg
xc9500_logo.jpg
............\......\xpla3_logo.jpg
xpla3_logo.jpg
............\tim
............\...\cpldta_glossary.htm
............\...\cpldta_style.css
............\...\genreport.htm
............\...\leftnav.htm
............\...\report.htm
............\...\timing_report.htm
............\...\toc.css
............\...\topnav.htm
work
...\@a@l@u
...\......\verilog.psm
...\......\_primary.dat
...\......\_primary.vhd
...\@c@l@a32
...\........\verilog.psm
...\........\_primary.dat
...\........\_primary.vhd
...\@c@l@a4
...\.......\verilog.psm
...\.......\_primary.dat
...\.......\_primary.vhd
...\@control
...\........\verilog.psm
...\........\_primary.dat
...\........\_primary.vhd
...\@data@mem
...\.........\verilog.psm
...\.........\_primary.dat
...\.........\_primary.vhd
...\@e@x@p@i@p@e_test_v
...\...................\verilog.psm
...\...................\_primary.dat
...\...................\_primary.vhd
...\@e@x_@m@e@mpipe
...\...............\verilog.psm
...\...............\_primary.dat
...\...............\_primary.vhd
...\@f@u
...\....\verilog.psm
...\....\_primary.dat
...\....\_primary.vhd
...\@h@d@u
...\......\verilog.psm
...\......\_primary.dat
...\......\_primary.vhd
...\@i@d@p@i@p@e_test_v
...\...................\verilog.psm
...\...................\_primary.dat
...\...................\_primary.vhd
...\@i@d_@e@xpipe
...\.............\verilog.psm
...\.............\_primary.dat
...\.............\_primary.vhd
...\@i@f_@i@dpipe
...\.............\verilog.psm
...\.............\_primary.dat
...\.............\_primary.vhd
...\@m@e@m@p@i@p@e_test_v
...\.....................\verilog.psm
...\.....................\_primary.dat
...\.....................\_primary.vhd
...\@m@e@m_@w@bpipe
...\...............\verilog.psm
...\...............\_primary.dat
...\...............\_primary.vhd
...\@m@i@p@s
...\........\verilog.psm
...\........\_primary.dat
...\........\_primary.vhd
...\@m@u@x_2to1
...\...........\verilog.psm
...\...........\_primary.dat
...\...........\_primary.vhd
...\@m@u@x_3to1
...\...........\verilog.psm
...\...........\_primary.dat
...\...........\_primary.vhd
...\@p@c
...\....\verilog.psm
...\....\_primary.dat
...\....\_primary.vhd
...\@p@c_test_v
...\...........\verilog.psm
...\...........\_primary.dat
...\...........\_primary.vhd
...\@registers
...\..........\verilog.psm
...\..........\_primary.dat
...\..........\_primary.vhd
...\@w@b@p@i@p@e_test_v
...\...................\verilog.psm
...\...................\_primary.dat
...\...................\_primary.vhd
...\alu_test_v
...\..........\verilog.psm
...\..........\_primary.dat
...\..........\_primary.vhd
...\cla_test_v
...\..........\verilog.psm
...\..........\_primary.dat
...\..........\_primary.vhd
...\control_test_v
...\..............\verilog.psm
...\..............\_primary.dat
...\..............\_primary.vhd
...\data_test_v
...\...........\verilog.psm
...\...........\_primary.dat
...\...........\_primary.vhd
...\glbl
...\....\verilog.psm
...\....\_primary.dat
...\....\_primary.vhd
...\reg_test_v
...\..........\verilog.psm
...\..........\_primary.dat
...\..........\_primary.vhd
...\_info
_ngo
...\netlist.lst
_xmsgs
.....\cpldfit.xmsgs
.....\hprep6.xmsgs
.....\ngdbuild.xmsgs
.....\taengine.xmsgs
.....\tsim.xmsgs
.....\xst.xmsgs
.lso
ALU.prj
ALU.stx
ALU.v
ALU.xst
alu_test.v
alu_test_v.udo
ALU_vhdl.prj
CLA32.v
CLA4.v
cla_test.v
cla_test_v.udo
Control.v
control_test.v
control_test_v.udo
DataMem.prj
DataMem.stx
DataMem.v
DataMem.xst
DataMem_vhdl.prj
data_test.v
data_test_v.fdo
data_test_v.udo
EXPIPE_test.v
EXPIPE_test_v.fdo
EXPIPE_test_v.udo
EX_MEMpipe.v
fu.v
HDU.prj
HDU.stx
hdu.v
HDU.xst
HDU_vhdl.prj
IDPIPE_test.v
IDPIPE_test_v.udo
ID_EXpipe.v
IF_IDpipe.prj
IF_IDpipe.stx
IF_IDpipe.v
IF_IDpipe.xst
IF_IDpipe_vhdl.prj
MEMPIPE_test.v
MEMPIPE_test_v.udo
MEM_WBpipe.prj
MEM_WBpipe.stx
MEM_WBpipe.v
MEM_WBpipe.xst
MEM_WBpipe_vhdl.prj
MIPS.cmd_log
mips.ise
mips.ise_ISE_Backup
MIPS.lso
MIPS.ngr
MIPS.prj
mips.restore
MIPS.syr
MIPS.udo
MIPS.v
MIPS.xst
mips_ise9migration.zip
MIPS_vhdl.prj
mux.v
MUX_2to1.bld
MUX_2to1.chk
MUX_2to1.cxt
MUX_2to1.gyd
MUX_2to1.jed
MUX_2to1.log
MUX_2to1.mfd
MUX_2to1.nga
MUX_2to1.ngc
MUX_2to1.ngd
MUX_2to1.ngr
MUX_2to1.pad
MUX_2to1.pnx
MUX_2to1.prj
MUX_2to1.rpt
MUX_2to1.stx
MUX_2to1.tim
MUX_2to1.tspec
MUX_2to1.vm6
MUX_2to1.xml
MUX_2to1.xst
MUX_2to1_build.xml
MUX_2to1_pad.csv
MUX_2to1_vhdl.prj
PC.udo
PC.v
PC_test.v
PC_test_v.fdo
PC_test_v.udo
Registers.prj
Registers.stx
Registers.v
Registers.xst
Registers_vhdl.prj
reg_test.v
reg_test_v.fdo
reg_test_v.udo
tmperr.err
transcript
vsim.wlf
WBPIPE_test.v
WBPIPE_test_v.udo
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