it is xilinx SDR SDRAM controller core




File list:
verilog
......\func_sim
......\........\func_sim.cfg
......\........\func_sim.log
......\........\func_sim.vpd
......\........\run_sim
......\........\string_decode_fn.v
......\........\tb_sdrm.v
......\micron
......\......\bank0.txt
......\......\bank1.txt
......\......\mt48lc1m16a1-8a.v
......\......\mt48lc1m16a1.v
......\......\test.v
......\par
......\...\run_par
......\...\sdrm.edf
......\...\sdrm.ucf
......\...\sdrm_par.sdf
......\...\sdrm_par.v
......\post_route
......\..........\post_route.cfg
......\..........\post_route.log
......\..........\post_route.vpd
......\..........\run_sim
......\..........\sdrm_par.sdf
......\..........\sdrm_par.v
......\..........\string_decode_post_route.v
......\..........\tb_post_route.v
......\src
......\...\brst_cntr.v
......\...\cslt_cntr.v
......\...\define.v
......\...\ki_cntr.v
......\...\rcd_cntr.v
......\...\ref_cntr.v
......\...\sdrm.v
......\...\sdrmc_state.v
......\...\sdrm_t.v
......\...\sys_int.v
......\synth
......\.....\run_synth
......\.....\sdrm.edf
......\.....\sdrm.scr
......\.....\setup.scr
......\README