verilog_lecture Verilog basic useful for verilog beginners. - source code download

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verilog_lecture

Classification:Hardware/embedded - VHDL Develop Development Tool:VHDL Sise:1.14 MB Upload time:2012/7/3 6:50:26 Uploader:asdfgh321 Download Statistics:

Description

Verilog basic useful for verilog beginners.

File list:
verilog_lecture
..............\lab
..............\...\lab1
..............\...\....\add16.v
..............\...\lab10
..............\...\.....\test_pli.v
..............\...\.....\veriuser.c
..............\...\lab4
..............\...\....\clk_chain.sdf
..............\...\....\clk_chain.v
..............\...\lab5
..............\...\....\case.v
..............\...\....\design.sdf
..............\...\....\design.v
..............\...\....\ifthen.v
..............\...\....\multi_bit_access.v
..............\...\....\single_word_access.v
..............\...\lab9
..............\...\....\violation.v
..............\lab_solution
..............\............\lab1
..............\............\....\add16.v
..............\............\lab2
..............\............\....\add16.v
..............\............\....\mulitplier.v
..............\............\....\mulitplier_add.v
..............\............\....\top.v
..............\............\lab3
..............\............\....\lab3.v
..............\............\lab4
..............\............\....\clk_chain.sdf
..............\............\....\clk_chain.v
..............\............\lab5
..............\............\....\case.v
..............\............\....\design.sdf
..............\............\....\design.v
..............\............\....\ifthen.v
..............\............\....\multi_bit_access.v
..............\............\....\single_word_access.v
..............\............\lab6
..............\............\....\add16.v
..............\............\....\mulitplier_add.v
..............\............\....\top.v
..............\............\lab7
..............\............\....\binary
..............\............\....\......\state.v
..............\............\....\......\top.v
..............\............\....\one-hot
..............\............\....\.......\state_onehot.v
..............\............\....\.......\top_onehot.v
..............\............\lab8
..............\............\....\initial.v
..............\............\lab9
..............\............\....\mux2.v
..............\............\....\violation.v
..............\verilog_lecture.ppt

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