veriloge course




File list:
VERILOG_COURSE
.............\on-line_ref_guide
.............\.................\README.txt
.............\.................\vlog_ref_body.html
.............\.................\vlog_ref_toc.html
.............\.................\vlog_ref_top.html
.............\Synthesis Templates
.............\...................\barrel shifter.v
.............\...................\Comparator,.v
.............\...................\Counter.v
.............\...................\Decoder.v
.............\...................\Encoder.v
.............\...................\FlipFlops.v
.............\...................\Latches.v
.............\...................\Multiplexer.v
.............\...................\Others.v
.............\...................\Ram.v
.............\...................\ShiftReg.v
.............\...................\StandAloneStandard.v
.............\...................\StateMachin.v
.............\...................\transcript
.............\10_DesignFlow.pdf
.............\11_FP-SOC.pdf
.............\1_Introduction.pdf
.............\2_Design.pdf
.............\3_ASICDesign.pdf
.............\4_PLD.pdf
.............\5_FPGA.pdf
.............\6_Altera EPLD.pdf
.............\7_Altera FPGA.pdf
.............\8_Xilinx FPGA.pdf
.............\9_Actel FPGA.pdf
.............\cash register-param.v
.............\cash register.v
.............\dice-bevavioral.v
.............\dice-dataflow.v
.............\dice.pdf
.............\Fsm.v
.............\mult1.v
.............\mult2.v
.............\mult3.v
.............\Verilog 1.pdf
.............\Verilog 2.pdf
.............\Verilog 3.pdf
.............\Verilog 4.pdf
.............\Verilog 5.pdf
.............\Verilog 6.pdf
.............\Verilog 7.pdf